| Message ID | 20221212115505.36770-5-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | AX45MP: Add support to non-coherent DMA | expand |
Hi Geert, On Tue, Dec 13, 2022 at 5:15 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Dec 12, 2022 at 12:55 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Pass direction and operation to ALT_CMO_OP() macro. > > > > Vendors might want to perform different operations based on the direction > > and callbacks (arch_sync_dma_for_device/arch_sync_dma_for_cpu/ > > arch_dma_prep_coherent) so to handle such cases pass the direction and > > operation to ALT_CMO_OP() macro. This is in preparation for adding errata > > for the Andes CPU core. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/arch/riscv/include/asm/errata_list.h > > +++ b/arch/riscv/include/asm/errata_list.h > > @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE( \ > > #define THEAD_flush_A0 ".long 0x0275000b" > > #define THEAD_SYNC_S ".long 0x0190000b" > > > > -#define ALT_CMO_OP(_op, _start, _size, _cachesize) \ > > +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ > > Since commit a49ab905a1fc8630 ("RISC-V: Implement arch specific PMEM > APIs") in riscv/for-next, there are two new users of this macro, > which need to be updated to (add two zeroes?). > Thanks for pointing that out, I'll rebase on for-next. I think -1 would be a better option than zeros. Cheers, Prabhakar
Hey Prabhakar, On Mon, Dec 12, 2022 at 11:55:03AM +0000, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Pass direction and operation to ALT_CMO_OP() macro. > > Vendors might want to perform different operations based on the direction > and callbacks (arch_sync_dma_for_device/arch_sync_dma_for_cpu/ > arch_dma_prep_coherent) so to handle such cases pass the direction and > operation to ALT_CMO_OP() macro. This is in preparation for adding errata > for the Andes CPU core. This patch seems to break the build on top of the most recent linux-next: ......./stuff/linux/arch/riscv/mm/pmem.c:13:53: error: too few arguments provided to function-like macro invocation ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); ^ /stuff/linux/arch/riscv/include/asm/errata_list.h:127:9: note: macro 'ALT_CMO_OP' defined here #define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ ^ .. CC block/partitions/sgi.o .+...+/stuff/linux/arch/riscv/mm/pmem.c:13:2: error: use of undeclared identifier 'ALT_CMO_OP' ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); ^ /stuff/linux/arch/riscv/mm/pmem.c:19:53: error: too few arguments provided to function-like macro invocation ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); ^ /stuff/linux/arch/riscv/include/asm/errata_list.h:127:9: note: macro 'ALT_CMO_OP' defined here #define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ ^ ........... AR lib/math/built-in.a ./stuff/linux/arch/riscv/mm/pmem.c:19:2: .error: use of undeclared identifier 'ALT_CMO_OP' ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); ^ ..4 errors generated. The pmem stuff is new so that'd be why it has not come up before. (FWIW, clang allmodconfig) > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v4 -> v5 > * Updated commit message. > > RFC v3 -> v4 > * New patch > --- > arch/riscv/include/asm/cacheflush.h | 4 ++++ > arch/riscv/include/asm/errata_list.h | 8 ++++++-- > arch/riscv/mm/dma-noncoherent.c | 15 ++++++++++----- > 3 files changed, 20 insertions(+), 7 deletions(-) > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > index 03e3b95ae6da..e22019668b9e 100644 > --- a/arch/riscv/include/asm/cacheflush.h > +++ b/arch/riscv/include/asm/cacheflush.h > @@ -8,6 +8,10 @@ > > #include <linux/mm.h> > > +#define NON_COHERENT_SYNC_DMA_FOR_DEVICE 0 > +#define NON_COHERENT_SYNC_DMA_FOR_CPU 1 > +#define NON_COHERENT_DMA_PREP 2 > + > static inline void local_flush_icache_all(void) > { > asm volatile ("fence.i" ::: "memory"); > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index 2ba7e6e74540..48e899a8e7a9 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE( \ > #define THEAD_flush_A0 ".long 0x0275000b" > #define THEAD_SYNC_S ".long 0x0190000b" > > -#define ALT_CMO_OP(_op, _start, _size, _cachesize) \ > +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ > asm volatile(ALTERNATIVE_2( \ > __nops(6), \ > "mv a0, %1\n\t" \ > @@ -146,7 +146,11 @@ asm volatile(ALTERNATIVE_2( \ > ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ > : : "r"(_cachesize), \ > "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ > - "r"((unsigned long)(_start) + (_size)) \ > + "r"((unsigned long)(_start) + (_size)), \ > + "r"((unsigned long)(_start)), \ > + "r"((unsigned long)(_size)), \ > + "r"((unsigned long)(_dir)), \ > + "r"((unsigned long)(_ops)) \ > : "a0") > > #define THEAD_C9XX_RV_IRQ_PMU 17 > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c > index d919efab6eba..e2b82034f504 100644 > --- a/arch/riscv/mm/dma-noncoherent.c > +++ b/arch/riscv/mm/dma-noncoherent.c > @@ -19,13 +19,16 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, > > switch (dir) { > case DMA_TO_DEVICE: > - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); > + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size, > + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE); > break; > case DMA_FROM_DEVICE: > - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); > + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size, > + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE); > break; > case DMA_BIDIRECTIONAL: > - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); > + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size, > + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE); > break; > default: > break; > @@ -42,7 +45,8 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, > break; > case DMA_FROM_DEVICE: > case DMA_BIDIRECTIONAL: > - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); > + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size, > + dir, NON_COHERENT_SYNC_DMA_FOR_CPU); > break; > default: > break; > @@ -53,7 +57,8 @@ void arch_dma_prep_coherent(struct page *page, size_t size) > { > void *flush_addr = page_address(page); > > - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); > + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size, > + 0, NON_COHERENT_DMA_PREP); > } > > void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, > -- > 2.25.1 >
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 03e3b95ae6da..e22019668b9e 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -8,6 +8,10 @@ #include <linux/mm.h> +#define NON_COHERENT_SYNC_DMA_FOR_DEVICE 0 +#define NON_COHERENT_SYNC_DMA_FOR_CPU 1 +#define NON_COHERENT_DMA_PREP 2 + static inline void local_flush_icache_all(void) { asm volatile ("fence.i" ::: "memory"); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 2ba7e6e74540..48e899a8e7a9 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE( \ #define THEAD_flush_A0 ".long 0x0275000b" #define THEAD_SYNC_S ".long 0x0190000b" -#define ALT_CMO_OP(_op, _start, _size, _cachesize) \ +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ asm volatile(ALTERNATIVE_2( \ __nops(6), \ "mv a0, %1\n\t" \ @@ -146,7 +146,11 @@ asm volatile(ALTERNATIVE_2( \ ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ : : "r"(_cachesize), \ "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ - "r"((unsigned long)(_start) + (_size)) \ + "r"((unsigned long)(_start) + (_size)), \ + "r"((unsigned long)(_start)), \ + "r"((unsigned long)(_size)), \ + "r"((unsigned long)(_dir)), \ + "r"((unsigned long)(_ops)) \ : "a0") #define THEAD_C9XX_RV_IRQ_PMU 17 diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index d919efab6eba..e2b82034f504 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -19,13 +19,16 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, switch (dir) { case DMA_TO_DEVICE: - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size, + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE); break; case DMA_FROM_DEVICE: - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size, + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE); break; case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size, + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE); break; default: break; @@ -42,7 +45,8 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, break; case DMA_FROM_DEVICE: case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size, + dir, NON_COHERENT_SYNC_DMA_FOR_CPU); break; default: break; @@ -53,7 +57,8 @@ void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size, + 0, NON_COHERENT_DMA_PREP); } void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,