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[92.34.216.5]) by smtp.gmail.com with ESMTPSA id bg25-20020a05651c0b9900b0027fbd4ee003sm876925ljb.124.2022.12.27.15.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Dec 2022 15:04:12 -0800 (PST) From: Linus Walleij Date: Wed, 28 Dec 2022 00:03:36 +0100 Subject: [PATCH 4/7] crypto: stm32/hash: Make dma_mode a bool MIME-Version: 1.0 Message-Id: <20221227-ux500-stm32-hash-v1-4-b637ac4cda01@linaro.org> References: <20221227-ux500-stm32-hash-v1-0-b637ac4cda01@linaro.org> In-Reply-To: <20221227-ux500-stm32-hash-v1-0-b637ac4cda01@linaro.org> To: Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue , Lionel Debieve Cc: linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linus Walleij X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This flag enables/disables DMA mode and is a true/false flag so make it a bool. Clamp the value from the HASH_HWCFGR register to a bool as well using a double-bang construction. Signed-off-by: Linus Walleij --- drivers/crypto/stm32/stm32-hash.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/stm32/stm32-hash.c b/drivers/crypto/stm32/stm32-hash.c index cc0a4e413a82..5f03be121787 100644 --- a/drivers/crypto/stm32/stm32-hash.c +++ b/drivers/crypto/stm32/stm32-hash.c @@ -166,7 +166,7 @@ struct stm32_hash_dev { struct reset_control *rst; void __iomem *io_base; phys_addr_t phys_base; - u32 dma_mode; + bool dma_mode; u32 dma_maxburst; struct ahash_request *req; @@ -481,7 +481,7 @@ static int stm32_hash_hmac_dma_send(struct stm32_hash_dev *hdev) struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm); int err; - if (ctx->keylen < HASH_DMA_THRESHOLD || (hdev->dma_mode == 1)) { + if (ctx->keylen < HASH_DMA_THRESHOLD || (hdev->dma_mode)) { err = stm32_hash_write_key(hdev); if (stm32_hash_wait_busy(hdev)) return -ETIMEDOUT; @@ -568,7 +568,7 @@ static int stm32_hash_dma_send(struct stm32_hash_dev *hdev) sg[0] = *tsg; if (sg_is_last(sg)) { - if (hdev->dma_mode == 1) { + if (hdev->dma_mode) { len = (ALIGN(sg->length, 16) - 16); ncp = sg_pcopy_to_buffer( @@ -602,7 +602,7 @@ static int stm32_hash_dma_send(struct stm32_hash_dev *hdev) return err; } - if (hdev->dma_mode == 1) { + if (hdev->dma_mode) { if (stm32_hash_wait_busy(hdev)) return -ETIMEDOUT; reg = stm32_hash_read(hdev, HASH_CR); @@ -663,7 +663,7 @@ static bool stm32_hash_dma_aligned_data(struct ahash_request *req) return false; if (sg_nents(req->src) > 1) { - if (hdev->dma_mode == 1) + if (hdev->dma_mode) return false; for_each_sg(req->src, sg, sg_nents(req->src), i) { if ((!IS_ALIGNED(sg->length, sizeof(u32))) && @@ -1525,7 +1525,7 @@ static int stm32_hash_probe(struct platform_device *pdev) if (ret) goto err_engine_start; - hdev->dma_mode = stm32_hash_read(hdev, HASH_HWCFGR); + hdev->dma_mode = !!stm32_hash_read(hdev, HASH_HWCFGR); /* Register algos */ ret = stm32_hash_register_algs(hdev);