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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id s5-20020a170906c30500b008552bc8399dsm18410066ejz.172.2023.01.23.05.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 05:30:25 -0800 (PST) From: Luca Weiss Date: Mon, 23 Jan 2023 14:29:51 +0100 Subject: [PATCH v4 3/3] arm64: dts: qcom: sm6350: Use specific qmpphy compatible MIME-Version: 1.0 Message-Id: <20230120-sm6350-usbphy-v4-3-4d700a90ba16@fairphone.com> References: <20230120-sm6350-usbphy-v4-0-4d700a90ba16@fairphone.com> In-Reply-To: <20230120-sm6350-usbphy-v4-0-4d700a90ba16@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Johan Hovold X-Mailer: b4 0.12.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The sc7180 phy compatible works fine for some cases, but it turns out sm6350 does need proper phy configuration in the driver, so use the newly added sm6350 compatible. Because the sm6350 compatible is using the new binding, we need to change the node quite a bit to match it. This fixes qmpphy init when no USB cable is plugged in during bootloader stage. Reviewed-by: Johan Hovold Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 54 +++++++++++------------------------- 1 file changed, 16 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 8224adb99948..128dbbe23ef5 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -1314,49 +1315,26 @@ usb_1_hsphy: phy@88e3000 { resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sc7180-qmp-usb3-dp-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x40>, - <0 0x088ea000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1_qmpphy: phy@88e8000 { + compatible = "qcom,sm6350-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&xo_board>, - <&rpmhcc RPMH_QLINK_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB30_PRIM_GDSC>; - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: usb3-phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; + #clock-cells = <1>; + #phy-cells = <1>; - dp_phy: dp-phy@88ea200 { - reg = <0 0x088ea200 0 0x200>, - <0 0x088ea400 0 0x200>, - <0 0x088eaa00 0 0x200>, - <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>; - #phy-cells = <0>; - #clock-cells = <1>; - }; + status = "disabled"; }; dc_noc: interconnect@9160000 { @@ -1430,7 +1408,7 @@ usb_1_dwc3: usb@a600000 { snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; }; };