From patchwork Thu Jan 26 13:50:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 648259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C5CCC54E94 for ; Thu, 26 Jan 2023 13:52:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229848AbjAZNwq (ORCPT ); Thu, 26 Jan 2023 08:52:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229626AbjAZNwf (ORCPT ); Thu, 26 Jan 2023 08:52:35 -0500 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6B984B75C; Thu, 26 Jan 2023 05:52:31 -0800 (PST) Received: by mail-ej1-x62a.google.com with SMTP id v6so5207051ejg.6; Thu, 26 Jan 2023 05:52:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VLWjnSTFLXfe6SVbC8tZ0mAHrHhhFAe2dhJdqThxnA4=; b=ph+9bieDcGdbUODWJAui93a4TFqfJENFBgCWB3Mxt62PM+Sq30A6MGoSyq8/3fVTu6 R6DdherzSoVU8qSRE4x0lduB20NZaywWNgopH4zVM8Xrpn1dMUIPgtPke7Nu0c3JLj7R mzL86HEu6ei8FyNmT+Kxh8OMdUrERvie1iSXyhn2WzGbLvuAmQpQW//V+zLA6tUVOU6E 4YYVgCkdWLu6HO3ETuGYW83Oa4ELOCmarBZMgqs8O4WahyuOLb3wtZC+Y7chsU87p922 Tq7IY1VkQSJ1A7ciytSopbqgpq9dm5aNznibks33KaBJ9vbU2/uNHoYJMGVDSp2EV1Bd iVIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VLWjnSTFLXfe6SVbC8tZ0mAHrHhhFAe2dhJdqThxnA4=; b=3JZT7xec+aZrta7q6rA2VRZ+ckuwkiKf2EbH8jwlRRnp1EIXxklpTJc2p5AkYOeNxV MQcuN0d1A2pR6GMKYNR73LTr0wNdQ96ujV3hGmJleBzqo8a7DbJ5YJJ4Epkl1oOwP3Zj zkA+4KMRfFB/8CjmBGzB8HvtTIqpcctSeVbv25bISt09sTaHix1IRa3GdzPKp1c9MlQB 29IUQjblyT+XbRJFZvdyG46A7VvEB9nQZ4viUOef0sA45UJx0Z4rQlK+RhRZKqDBVIer F2qk5JG3TeFOUjtrznuvP2ld5dhnvOIq115zxomp5ZZx6wV777Z/rJUVVtz+CfNpVmV9 MFYw== X-Gm-Message-State: AFqh2kp8WOFj7M2L5LI9QBcX+ZtQ5FFsI34NWnmpem4cNxk/pPesSKxX GNBWFG/PBavrhewtwfBOb8I= X-Google-Smtp-Source: AMrXdXuTqvOwOguF+cFIH6I5/XrlifUMviSrlMs5CiT3D+atDlneE42KEVRBQXqTBNmhhg+LB76r8g== X-Received: by 2002:a17:906:6a81:b0:82d:e2a6:4b0d with SMTP id p1-20020a1709066a8100b0082de2a64b0dmr33593928ejr.18.1674741150020; Thu, 26 Jan 2023 05:52:30 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id t15-20020a508d4f000000b004a0e2fe619esm591611edt.39.2023.01.26.05.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:52:29 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, wenrui.li@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Rodrigo Vivi , Mikko Kovanen , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 2/8] PCI: rockchip: Fixed setup of Device ID Date: Thu, 26 Jan 2023 14:50:42 +0100 Message-Id: <20230126135049.708524-3-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230126135049.708524-1-rick.wertenbroek@gmail.com> References: <20230126135049.708524-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Device ID was written to a read-only register and therefore did not work. The Device ID is now updated through the correct register. This is documented in the RK3399 TRM section 17.6.6.1.1 Signed-off-by: Rick Wertenbroek --- drivers/pci/controller/pcie-rockchip-ep.c | 6 ++++-- drivers/pci/controller/pcie-rockchip.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index d5c477020..9b835377b 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -115,6 +115,7 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_header *hdr) { + u32 reg; struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; @@ -127,8 +128,9 @@ static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, PCIE_CORE_CONFIG_VENDOR); } - rockchip_pcie_write(rockchip, hdr->deviceid << 16, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); + reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID); + reg = (reg & 0xFFFF) | (hdr->deviceid << 16); + rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID); rockchip_pcie_write(rockchip, hdr->revid | diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 32c3a859c..51a123e5c 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -133,6 +133,8 @@ #define PCIE_RC_RP_ATS_BASE 0x400000 #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 #define PCIE_RC_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18