From patchwork Thu Feb 2 12:39:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 649835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC677C61DA4 for ; Thu, 2 Feb 2023 12:40:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232353AbjBBMkR (ORCPT ); Thu, 2 Feb 2023 07:40:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232239AbjBBMjx (ORCPT ); Thu, 2 Feb 2023 07:39:53 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 705488E04A for ; Thu, 2 Feb 2023 04:39:29 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id r2so1569974wrv.7 for ; Thu, 02 Feb 2023 04:39:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W8ipbXkSPL37n3A8t/Jal5T88LelKqVf60eLRmlYx4I=; b=yPFYZBDkdeU1SfbbI4WBoLvzuVyDqyurZo7Iv4WA07ahS9AlT7H9JooRpXEhWc8iQ2 d+/CKarwMrNaR52YnitdStMFvQVwRSC6Dww18dePwk/wNDuN+mypBJEGp2Zt0BzqPPbd Hryycf0C1QKErW2aZIyaUfKXhMjV8C+AxC4PNNdwRjNwFEqo1auMQViIVZ54kemprZRR hEVR+C2/IbTzd5bx+ARz+QinkZyFYtQplkTnuhGCtJPnas493f41jjazI3+yPbRq2/Ar Ur6GcgFbpJT2Xd11PnEzeoW0Iz8XNOqHZ8kIKjd5AqtxocpWB0eR6I5CHwkUgjCSBX8R qoiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W8ipbXkSPL37n3A8t/Jal5T88LelKqVf60eLRmlYx4I=; b=wepUKx2nM4dlTI4EUYq0DWHaSVO90mld/oZ9Y8uWZK72FxttFzBtqeLCnzCtO6WQaH JjaBAEm2TyOJdJ/+AptPrb1AkovC3h1/XIydrETnTIXa8v879+4jI4yyFJ7+y85/AXVW 4GnTb0ViMs0NVHWVgjN8ghI86K5dw11CqhqACzZ25NItS0ZnHSu7bcY8+K83R3qu7WeW 0c0+Dp2qKHvqg+c3G2zHQr+IHvn4jcKN/++Q7wkwh8Se22ObkdOHwncyNDDVuuCq4Hlm AZEAFdOZOpzHMvXDUKH+tQvhz1x4pAy67o6oMZ/iTlRozbL6eDUiJwGn0IUyXcucx0um eCwQ== X-Gm-Message-State: AO0yUKWMQLctA5nn1sa1fJy3VF2nU2rmQTcCjahvbKEdzVfnyUPUcZG3 Gas69L7X0tZBuPmB+PnUQl+vJQ== X-Google-Smtp-Source: AK7set+P0OqTh2slEdaZnFO4/olYoP/mCwp659pG1hQHxj/yEKy3FeBSAa0OML5p7Jj1lizYHmPQ5w== X-Received: by 2002:adf:ec0e:0:b0:2bf:b839:c486 with SMTP id x14-20020adfec0e000000b002bfb839c486mr5549655wrn.55.1675341568837; Thu, 02 Feb 2023 04:39:28 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id j5-20020adff005000000b002bddd75a83fsm19525644wro.8.2023.02.02.04.39.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 04:39:28 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Neil Armstrong Subject: [PATCH v6 12/12] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes Date: Thu, 2 Feb 2023 14:39:02 +0200 Message-Id: <20230202123902.3831491-13-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202123902.3831491-1-abel.vesa@linaro.org> References: <20230202123902.3831491-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable PCIe controllers and PHYs nodes on SM8550 MTP board. Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa --- This patch does not have a v3, but since it is now part of the same patchset with the controller and the phy drivers patches, I had to bump the version to 4. The v5 was here: https://lore.kernel.org/all/20230124124714.3087948-13-abel.vesa@linaro.org/ Changes since v5: * none Changes since v4: * moved here the pinctrl properties and out of dtsi file Changes since v2: * none Changes since v1: * ordered pcie related nodes alphabetically in MTP dts * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes * dropped the child node from the phy nodes, like Johan suggested, and updated to use the sc8280xp binding scheme * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy to "nocsr" * reordered all pcie nodes properties to look similar to the ones from sc8280xp arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 38 +++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index e756f83a941c..265862d0e44f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -407,6 +407,44 @@ &mdss_mdp { status = "okay"; }; +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p91>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; + + status = "okay"; +}; + &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins = "gpio12";