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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id s13-20020a5d510d000000b002d64fcb362dsm4020432wrt.111.2023.04.07.02.34.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 02:34:32 -0700 (PDT) From: Alexandre Mergnat Date: Fri, 07 Apr 2023 11:34:17 +0200 Subject: [PATCH v3 6/7] arm64: dts: mediatek: add larb support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20230207-iommu-support-v3-6-97e19ad4e85d@baylibre.com> References: <20230207-iommu-support-v3-0-97e19ad4e85d@baylibre.com> In-Reply-To: <20230207-iommu-support-v3-0-97e19ad4e85d@baylibre.com> To: Yong Wu , Krzysztof Kozlowski , Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Krzysztof Kozlowski Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2919; i=amergnat@baylibre.com; h=from:subject:message-id; bh=/eg96dGEgFTbseacSYltO+tu8R5mtjKMtqf32ClmdXM=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkL+OhAHQ1FqZYfC72oBjPFXJ5fQNLH9cxIalmzV/J ZfLtvduJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZC/joQAKCRArRkmdfjHURWsEEA DE/WrZfKEfR7OQxQ2VlvgVUR/0jjuKcg7X2Cgh9UAltf6sQT+Hbj66w1Ty9fv3rTvNU4N7Anhzv5pE hy4NXMYoRO/+qVnfkIMQLQDLZffN799KGzWbh/xNfhH3exmfCuTQ2emeDGrAUZ8bFXJH/v0RGp45S2 9e2UBjmy5ib0xKBi9P8lKmx2mS50YhNTAaihC1jitXfALrfc6HP/FikAQSlY+BFiX9hDYwwYURaX2i o60+B+ymNVmUsCw0SLtWdN4YN0uClPbaYdVCIFYMmlqJVAAaPCfqLiF1YxPViWaLVuTmS3Ylw/Cq/v KFClmwOEVxo49P//NQWu0n/7K5+i+XAwo6SvDWucr5O42YnXJDD5w7YMk2nqzeC5mb7ctyjBZkkXlg KxQQ44dn6DHX+XY29ATDNwKdBcEWYpTxqWYNB+ZxE0fiuVkQTpLvMARpRp9S4ortu5CvNitzvgp9wx zvCZXu/aQfkSP2juKeiqqD/4il65nNPd00U1/a8ioixNEMOMcfyvj4QSLSkj75thT1VXNAvIx4XZrF dP7KV5tABzRJ7eOEWw9iyjS4YgdMRIjaAEMrXCHAxMiQkDwN0EqrOrrq+3kCf/y3Okdfq/bAP5jk5P LnDm9fAeFPQoj/KGk9XZg24wAJLMMInusHgU7H2pfxLZ9zC4DPQYcZpqutLg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Local arbiter (LARB) is a component of Smart Multimedia Interface (SMI), used to help the memory management (IOMMU). This patch add 4 LARBs and 2 clocks for the larb1 and larb3 support. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 59 ++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 70915beb513c..07a7267f338e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -724,12 +724,71 @@ smi_common: smi@14002000 { power-domains = <&spm MT8365_POWER_DOMAIN_MM>; }; + larb0: larb@14003000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + mediatek,larb-id = <0>; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; + larb2: larb@15001000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_MM_SMI_IMG>, + <&camsys CLK_CAM_LARB2>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + mediatek,larb-id = <2>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8365-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb3: larb@16010000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_LARB1>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; + mediatek,larb-id = <3>; + }; + + vencsys: syscon@17000000 { + compatible = "mediatek,mt8365-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb1: larb@17010000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; + mediatek,larb-id = <1>; + }; + apu: syscon@19020000 { compatible = "mediatek,mt8365-apu", "syscon"; reg = <0 0x19020000 0 0x1000>;