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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id s13-20020a5d510d000000b002d64fcb362dsm4020432wrt.111.2023.04.07.02.34.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 02:34:33 -0700 (PDT) From: Alexandre Mergnat Date: Fri, 07 Apr 2023 11:34:18 +0200 Subject: [PATCH v3 7/7] arm64: dts: mediatek: add iommu support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20230207-iommu-support-v3-7-97e19ad4e85d@baylibre.com> References: <20230207-iommu-support-v3-0-97e19ad4e85d@baylibre.com> In-Reply-To: <20230207-iommu-support-v3-0-97e19ad4e85d@baylibre.com> To: Yong Wu , Krzysztof Kozlowski , Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Krzysztof Kozlowski Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1094; i=amergnat@baylibre.com; h=from:subject:message-id; bh=DnJEBHRsbqHL6qyjSRQDzaDxfH+izMrFh6xvaojG8T4=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkL+Ohg0L1C33TWbvz3zKaLZwmTsLFe1MkCtyZMLpe Ti6X3s+JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZC/joQAKCRArRkmdfjHURZN1D/ 9aluz//LTMCYnheiQnLj++jXjk9/55KstgFzy9l/ZWVHcvv8qQgM37m3sxH+YQNW6PJHEUlYzA/75K dTUyKBiuWeqMB4BOwQo562DAf1kNBKsF5JcYN4fB0pjA4o5n4m+vzcZKAmtE81cPCrWO+Z680f7rod BLI9n/dMaWMSLeII7jmm2Npbe5D8hwifuSO9AUR06joR9hoGb/cDy1eOoehhAj5IPJk0P248cYB1Ri o+ThpClfOsU7f22gCusbilqxsw2AXhtW0OnUsfycFnXlzX5Z5EFCzIMJq3AzoUSTZcwD/0umfLMn5Z 0IfscdgMC/LtaEU5lHtjnj3b0nut0f43D++w9tUJJ/Np3HF9L/OIzb4kDE0HYBo1HNAAFiQHXRZIqf 3meLX+WJEi+cz8PgFkhmaFS47aAwoe/VlD4BQ3c4Q0O6nuctY/EYQVecHMbtGa6asRpdpSWV6td/15 FpfUITZap/juI5/Ll13V5MSfEbyH7+iE6qeeQo+GPdatetwyfuEoyQr4yV/tyUVDul0N/PtpwgrdKn FznOxUto/U6TBCeK9lh2DHw177IOmvD1ChDGCh4XpHDVUfNlnf5JF/tQ0t5bX295u22eNxSsZWEEQW jDnOWlcyNfLFUjdW3Wud9AwSiji2/arQFTmDrfqUDHwUhnVKbm+7MzULNntA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add iommu support in the SoC DTS using the 4 local arbiters (LARBs) Reviewed-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 07a7267f338e..6260744f4be5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -456,6 +456,14 @@ sysirq: interrupt-controller@10200a80 { reg = <0 0x10200a80 0 0x20>; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt8365-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; + #iommu-cells = <1>; + }; + infracfg_nao: infracfg@1020e000 { compatible = "mediatek,mt8365-infracfg", "syscon"; reg = <0 0x1020e000 0 0x1000>;