From patchwork Thu Feb 23 13:43:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 657333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABCB8C636D6 for ; Thu, 23 Feb 2023 13:44:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234396AbjBWNoH (ORCPT ); Thu, 23 Feb 2023 08:44:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234073AbjBWNoE (ORCPT ); Thu, 23 Feb 2023 08:44:04 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97740515CA; Thu, 23 Feb 2023 05:44:02 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A393F6602206; Thu, 23 Feb 2023 13:44:00 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1677159841; bh=6g8YPvF/fQJS5t/oA/EETjTk+HQtvnCv6Vgp6i8eIQg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=olJwAFq8rMEugAKgzqCigXxF1lW8Eay1JbWHmSlV4HDskIQBZrXRRRAWAow44fToM vNkjU+8q22aZ3/MqahFDM8H+XSNRafzhCkx2SkpoSX6b6OZWGqTJvxQ/iBOVp2Lo2E 9RKGGai6eQVK0spdDPwBmK60c+fb6eUNdvVq4tvZ+xI9IbM2juHB/De/rUSh3J6PpT 483cZXpcC/YXHTg/5dWDLfwLlqn/g1eb0tccKs4zvO9yP0h8twNP0hK3+9tkR9wCCh OZzB5+8KC6sc/lzOQ64UW16bsDx2O6f3guAT5XESplrs/fR2BhlhrxuyIh27Wnh/kE QX7qEFTv3D3ZA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH v2 08/16] arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain Date: Thu, 23 Feb 2023 14:43:37 +0100 Message-Id: <20230223134345.82625-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230223134345.82625-1-angelogioacchino.delregno@collabora.com> References: <20230223134345.82625-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The mfg_ref_sel clock is a mux used to switch between different "safe" (and slower) clock sources for the GPU: this is used during MFGPLL reconfiguration and eventually during idling at very low frequencies. This clock getting turned off means that the GPU will occasionally be unclocked, producing obvious consequences such as system crash or unpredictable behavior: assigning it to the top level MFG power domain will make sure that this stays on at all times during any operation on the MFG domain (only GPU-related transactions). Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 2a3606f68ae4..018d48f7d3c6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -499,8 +499,9 @@ power-domain@MT8192_POWER_DOMAIN_CONN { power-domain@MT8192_POWER_DOMAIN_MFG0 { reg = ; - clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; - clock-names = "mfg"; + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, + <&topckgen CLK_TOP_MFG_REF_SEL>; + clock-names = "mfg", "alt"; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>;