From patchwork Tue Feb 28 10:47:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 657566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 711BFC7EE2E for ; Tue, 28 Feb 2023 10:48:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231219AbjB1KsP (ORCPT ); Tue, 28 Feb 2023 05:48:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231160AbjB1KsG (ORCPT ); Tue, 28 Feb 2023 05:48:06 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69A4EA5FB; Tue, 28 Feb 2023 02:47:56 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id C54BB6602FD8; Tue, 28 Feb 2023 10:47:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1677581275; bh=/37a11W4Djj29RkQI1F06mX5BvaAyxmllH1tjzesJsU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jUnwV8DkKYgp0efQlZ3Av9SsbY6lnJiN2sKcpLo/e4f3yhDfgFMfut41lHFFvxFJF 7ZaNMdC5qXqThl/VOOPyDJdTSvotOxLx6I+hQtMNgy2AOkVx3GjwHFHi9BUzXETiSn D9Htts/fzp+ZHMRu8u0SVAE1T0LxZOfO3pjH4tZ4b1omL8+eroO8SAU9tvIIYkpV4X HuZP6Nfj14F9VHdUOvoAnRyABirJJRD/x+vGKaHFNDPmpbXHv/adsWc7yVjjjBVEXK OcUP987PtCzd+cLJT+jhhJzO5sBuqKgFmsGi+MD9ec7pmuT6yg/NL2+TSUsQSBe5Yt 1NNvMZLvyqSAg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org, =?utf-8?b?TsOtY29s?= =?utf-8?b?YXMgRi4gUi4gQS4gUHJhZG8=?= Subject: [PATCH v3 09/18] arm64: dts: mediatek: mt8192-asurada: Add MFG0 domain supply Date: Tue, 28 Feb 2023 11:47:32 +0100 Message-Id: <20230228104741.717819-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230228104741.717819-1-angelogioacchino.delregno@collabora.com> References: <20230228104741.717819-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nícolas F. R. A. Prado The mfg0 power domain encompasses the whole GPU and its surrounding glue logic. This power domain has a separate power rail. Add its power supply for Asurada. Signed-off-by: Nícolas F. R. A. Prado [wenst@chromium.org: fix subject prefix and add commit message] Signed-off-by: Chen-Yu Tsai [Angelo: Reordered commits to address DVFS stability issues] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 4 ++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 9f12257ab4e7..ec013d5ef157 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -380,6 +380,10 @@ &i2c7 { pinctrl-0 = <&i2c7_pins>; }; +&mfg0 { + domain-supply = <&mt6315_7_vbuck1>; +}; + &mipi_tx0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a29cdff8a095..f19d4a8ef3f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -497,7 +497,7 @@ power-domain@MT8192_POWER_DOMAIN_CONN { #power-domain-cells = <0>; }; - power-domain@MT8192_POWER_DOMAIN_MFG0 { + mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { reg = ; clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, <&topckgen CLK_TOP_MFG_REF_SEL>;