From patchwork Wed Mar 15 09:03:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 664299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ACD0C6FD1D for ; Wed, 15 Mar 2023 09:04:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229892AbjCOJES (ORCPT ); Wed, 15 Mar 2023 05:04:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229656AbjCOJEQ (ORCPT ); Wed, 15 Mar 2023 05:04:16 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F8F52CC6C; Wed, 15 Mar 2023 02:03:52 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32F93gNr127353; Wed, 15 Mar 2023 04:03:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1678871022; bh=pNYjOPZLfTGHtUQIJS1+TCtBaAmBtJH01h9FWZ4IfQc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tcsvrlEU8wSCjYkQb9ti1idRRqNTe0WVV+UUZF8BMgeUKPgG8Fre7KlfWXbxmOKdm iH47s4rSE3I49gKwUQDqGIAvW76cYfwaytRgRoOjTgvSqS+8k4/xlZUaGH2lsjFw1O TXutjzRLV+pabNsmm0IIKBuyGZoNkiXkNjHp6kaY= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32F93grZ068228 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Mar 2023 04:03:42 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 15 Mar 2023 04:03:41 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 15 Mar 2023 04:03:41 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32F93fTY104696; Wed, 15 Mar 2023 04:03:41 -0500 From: Jai Luthra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Mark Brown CC: , , , Andrew Davis , Jayesh Choudhary , Devarsh Thakkar , Aradhya Bhatia , Jai Luthra Subject: [PATCH v6 2/6] arm64: dts: ti: k3-am62-main: Add McASP nodes Date: Wed, 15 Mar 2023 14:33:31 +0530 Message-ID: <20230313-mcasp_upstream-v6-2-77685d7cbeb8@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230313-mcasp_upstream-v6-0-77685d7cbeb8@ti.com> References: <20230313-mcasp_upstream-v6-0-77685d7cbeb8@ti.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2740; i=j-luthra@ti.com; h=from:subject:message-id; bh=0fD4RCKgRcyT90JHKtvgV3Ukjm3btUjTWtPkMvr2fQE=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBkEYdXP14+js+tZYpFg8pyCv3M+O2Uv+BJf+iyX e6f5WZzIoGJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZBGHVwAKCRBD3pH5JJpx RWH4D/9LfrXZS9pnZAmF+QTx0tlZQEH4/NeXBuLSllaR6R9B/8RJ1xpM1k7VCHlz7B3XKIqJAZy VDft4OyhobE2CMCyNr2+Bova98JztxGvOwcHRJ5ylD9HbNlxpPOgUiR2b/0GYgMjNwHOgC1yx6R F2doBG4cd64Zi0soUQGH1b+DSL6X8/XDpNJl/cw8iLI7V1F4i2BqHrm7TqFskCoILsYW7Cr3x+Z Uh6A3/0oerIZtrmDkkuLqE/umF88O8Jar140o/DaNTW0kTDI/ckS13G+gkruQJA5i9nmaCTUVxl HaOA9IkRdwmW1GhZ+IoDk5OgAli5O8fLXc6IZ+TR9nd7Ez44jUjHPtwHo1ED2l7ydIqmEdFG4WZ L+FULqV+Ng1jG3oU1prTl5fmQN7okVrqUKYtjqiZOfdjnKI+P3RMitILYFVuA326lsumNjIr40C DdsL8H6eGmWv0JbHEp4lEMpDyURn5jNEoQO+dyvNChKWmPhHkWDSJld35dmS+hOssZ5w8MYmVOP 4O/PGi/CpVm8Lv39WwEwLzl5GIrK0amDvp4J+o8s44Z7Fpg4qWiS/vU2HENyRwa3B4dd2AGlzQW vu1REZ8LcBaj6mDw21ZRo88COkHSYAOZG6TjjwDPinIy31QncTk43XZw5/DIhYhMvNnJDYzULBK Nlmm4gBem/R1knw== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jayesh Choudhary Add the nodes for McASP 0-2. Use the audio-friendly 96MHz main_1_hsdivout6_clk as clock parent instead of the default 100Mhz main_2_hsdivout8_clk source. Signed-off-by: Jayesh Choudhary Signed-off-by: Jai Luthra Reviewed-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 60 ++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index ea683fd77d6a..c52c23ac409a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -787,4 +787,64 @@ epwm2: pwm@23020000 { clock-names = "tbclk", "fck"; status = "disabled"; }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 190 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 190 0>; + assigned-clock-parents = <&k3_clks 190 2>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 191 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 191 0>; + assigned-clock-parents = <&k3_clks 191 2>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 192 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 192 0>; + assigned-clock-parents = <&k3_clks 192 2>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; };