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[2001:470:1f10:aed::2]) by smtp.googlemail.com with ESMTPSA id h8-20020a6b7a08000000b00746041ecbf9sm1174834iom.39.2023.03.18.01.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Mar 2023 01:37:54 -0700 (PDT) From: Tianling Shen To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Jagan Teki , Peter Geis , Andy Yan , Tianling Shen , Brian Norris , Chris Morgan , Sebastian Reichel , Andrew Lunn , Michael Riesch , Maya Matuszczyk , Andrew Powers-Holmes , Sascha Hauer , Vasily Khoruzhick Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] arm64: dts: rockchip: fix gmac support for NanoPi R5S Date: Sat, 18 Mar 2023 16:37:44 +0800 Message-Id: <20230318083745.6181-5-cnsztl@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230318083745.6181-1-cnsztl@gmail.com> References: <20230318083745.6181-1-cnsztl@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org - Changed phy-mode to rgmii. - Fixed pull type in pinctrl for gmac0. - Removed duplicate properties in mdio node. These properties are defined in the gmac0 node already. Fixes: c6629b9a6738 ("arm64: dts: rockchip: Add FriendlyElec Nanopi R5S") Signed-off-by: Tianling Shen --- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts index e9adf5e66529..2a1118f15c29 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -57,7 +57,7 @@ &gmac0 { assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; phy-handle = <&rgmii_phy0>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 @@ -79,9 +79,6 @@ rgmii_phy0: ethernet-phy@1 { reg = <1>; pinctrl-0 = <ð_phy0_reset_pin>; pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; }; }; @@ -115,7 +112,7 @@ &pcie3x2 { &pinctrl { gmac0 { eth_phy0_reset_pin: eth-phy0-reset-pin { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; }; };