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Mon, 20 Mar 2023 11:27:13 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Mon, 20 Mar 2023 11:27:12 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.5 via Frontend Transport; Mon, 20 Mar 2023 11:27:07 -0700 From: Sumit Gupta To: , , , , , , , CC: , , , , , , , , , , , , , Subject: [Patch v3 11/11] memory: tegra186-emc: fix interconnect registration race Date: Mon, 20 Mar 2023 23:54:41 +0530 Message-ID: <20230320182441.11904-12-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230320182441.11904-1-sumitg@nvidia.com> References: <20230320182441.11904-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT056:EE_|PH0PR12MB8125:EE_ X-MS-Office365-Filtering-Correlation-Id: 6a67cb8c-72c5-40e4-4494-08db2970bf00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2023 18:27:21.9349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a67cb8c-72c5-40e4-4494-08db2970bf00 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8125 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The current interconnect provider registration interface is inherently racy as nodes are not added until the after adding the provider. This can specifically cause racing DT lookups to fail. Switch to using the new API where the provider is not registered until after it has been fully initialised. Fixes: ("memory: tegra: add interconnect support for DRAM scaling in Tegra234") Signed-off-by: Sumit Gupta --- drivers/memory/tegra/tegra186-emc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 0d68a20fd376..a5a2bce01db4 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -207,15 +207,13 @@ static int tegra_emc_interconnect_init(struct tegra186_emc *emc) emc->provider.xlate = tegra_emc_of_icc_xlate; emc->provider.get_bw = tegra_emc_icc_get_init_bw; - err = icc_provider_add(&emc->provider); - if (err) - goto err_msg; + icc_provider_init(&emc->provider); /* create External Memory Controller node */ node = icc_node_create(TEGRA_ICC_EMC); if (IS_ERR(node)) { err = PTR_ERR(node); - goto del_provider; + goto err_msg; } node->name = "External Memory Controller"; @@ -236,11 +234,13 @@ static int tegra_emc_interconnect_init(struct tegra186_emc *emc) node->name = "External Memory (DRAM)"; icc_node_add(node, &emc->provider); + err = icc_provider_register(&emc->provider); + if (err) + goto remove_nodes; + return 0; remove_nodes: icc_nodes_remove(&emc->provider); -del_provider: - icc_provider_del(&emc->provider); err_msg: dev_err(emc->dev, "failed to initialize ICC: %d\n", err);