From patchwork Thu Mar 23 00:06:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 666358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA042C74A5B for ; Thu, 23 Mar 2023 00:11:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230445AbjCWALC (ORCPT ); Wed, 22 Mar 2023 20:11:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230059AbjCWAKv (ORCPT ); Wed, 22 Mar 2023 20:10:51 -0400 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4DA231E37; Wed, 22 Mar 2023 17:10:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hyNKk2EPWia4ZUVAsbcMelXnyckZilv+8G2tWYXIXbi2aMasVlRVlvah5OUHg5YcN/f6D7MjafwoPiD9qNThA97qhJsiCi6zMjK88PYAv82B+2TUjoxd/cTYCnmOaUotnOF1vvr0cwdpKUXrXUVPwzqdpQjgeRUkbDuyXZwU+dp3hNrLQRoADWMJUu8e/dG7XcoeKa0SY06HwUB7ernxozUhzier0vYfQUlizmXZDoHbnSGpQyUNqDaB3dBNbje6x75Fry1u6VyE2cYjGxlsNZc+8N2I+HQj9N17pIt4JlvKSefWpeADm7u/FZmKwb2NgtVG5LCPf1Fos0OUV34Zzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ymfACAjSLWbCk+4U3bvrCLTQlZYsf0VDrwtsvVsOjLE=; b=FJ+WqYs3Abl+R9eY++HiNPWqRkSfxE5iXyaEGtO0GCo0mlxZqT9V1VaNMnGbe5V7tLeInqSENzokUPIY57IHfspEa7UXicHcBOo37ViSFiJRqjfb5oJbi/DdNUmqcB3PgIv81RbFqX5jbQT0Q3sRO9eOaf9sWUt6ySo0lxrbHlRwDfHFhKN0Z5QLhy4mUCcsgeMzxBifWBedO4yCBq+pVfLeLc1i4Hi+lz0cKmK6T4zI03p6HmaDfYbDzvKBBNXvnUe32mch1Ex2ofFlrj/izWpFEQ7AhYFnv4CbmtT52W/hKVtBePt9ihcmStIq4izGESCwyhPllBRcG+0ZBHqteA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.infradead.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ymfACAjSLWbCk+4U3bvrCLTQlZYsf0VDrwtsvVsOjLE=; b=xQLmccMVPSGW8jo4cqx+mhrsNPBl+2FjvkQ1h0IBSSIfC0nQ7Mnz2Rd/ddDsSKxeZLCcxunIl0Jh3p98Uo1nc1nrRadxrXNtCepVwyfDp09I8VWXjUmYFeR74r2DA/mmKnAxOKnp1sSjbiA1EgN//WPCZPOaJotdjH7MNfS57v0= Received: from MN2PR11CA0012.namprd11.prod.outlook.com (2603:10b6:208:23b::17) by BL0PR12MB5506.namprd12.prod.outlook.com (2603:10b6:208:1cb::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.37; Thu, 23 Mar 2023 00:10:00 +0000 Received: from BL02EPF000100D0.namprd05.prod.outlook.com (2603:10b6:208:23b:cafe::67) by MN2PR11CA0012.outlook.office365.com (2603:10b6:208:23b::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.37 via Frontend Transport; Thu, 23 Mar 2023 00:10:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF000100D0.mail.protection.outlook.com (10.167.241.204) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6178.30 via Frontend Transport; Thu, 23 Mar 2023 00:10:00 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 22 Mar 2023 19:09:57 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 11/15] mmc: sdhci-cadence: Enable device specific override of writel() Date: Wed, 22 Mar 2023 17:06:53 -0700 Message-ID: <20230323000657.28664-12-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D0:EE_|BL0PR12MB5506:EE_ X-MS-Office365-Filtering-Correlation-Id: 0bdbfc15-741f-4fe6-6d47-08db2b32f1c4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uzI6ke5ikwd2dHSVTV1j9PvcvYw+A+eOGQYCx0oxrJ9DwoIpuQhLyCHj4djG4bb6HEVLds4+Jr6pljoUEYADapcZ8C3t7TXgvsud7sCiLj3q7M7F/lwoMxkbF2R4mmYQN5r3c/h0PaaNjJTQ99NCC6Yr2LQ4IrG8i46uftBKUUx3beqAsNNZnTZohHwA+U0D/MresNTPfQ5KXaWgL8rpiJ2IEqptGJ5k2mH0I3R/VSkhqpcHq1fZgTKlOhrO0Mj14QvBx1sfb7ZFBsycoT0oLeNgpafdE7pOrbtl2lb5KlBz0DwlZgBYYw5qClYbSmEcEznG35XDi+P9JKSFrTpTBXz3/H6fqE06a0dcdk3c5EsEsAidCB2kagWcMOUGTJNxy+0bGd77cS0jlpKIvYtrpvL2uqO4uefjVQ7X8RLgDwa+KgaDCKKtE7lQjHlFUCDVh+U+e3tezBKjpYTvl+39ice/Fe1FLcQM7pCsKjsioJhyMMrrWr5E0biPWrGe3Ea5StIr+yj63vjV1JgyMIW9ACa7uET7FqgE5BoabTYJ05lEKv862wvvoOE6ZpepOArpKBG7/itJUlnX4KWnpITiN3DNP6YvvjjZfeegrhmAoKzTS0NJHF3EYTSg0vCpAhFsmL7OvmxIesxUxuqs5HVFzGcGnwXXgYwb9k8Q0cVTF4bA6CYEWdphijHKOyxeKm1LwJZyYjjRmf/X1nh84VfIUKJ7iVFGsGOEJZSjJ2nARVQ= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(396003)(136003)(346002)(39860400002)(376002)(451199018)(46966006)(40470700004)(36840700001)(7416002)(5660300002)(8936002)(7406005)(41300700001)(36860700001)(82310400005)(40480700001)(36756003)(356005)(40460700003)(82740400003)(81166007)(2906002)(47076005)(16526019)(336012)(1076003)(83380400001)(6666004)(426003)(478600001)(2616005)(186003)(26005)(4326008)(54906003)(316002)(70206006)(8676002)(6916009)(70586007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 00:10:00.6973 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0bdbfc15-741f-4fe6-6d47-08db2b32f1c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB5506 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SoCs with device specific Cadence implementation, such as setting byte-enables before the write, need to override writel(). Add a callback where the default is writel() for all existing chips. Signed-off-by: Brad Larson Acked-by: Adrian Hunter --- v10 changes: - The 1st patch adding private writel() is unchanged. The 2nd patch is split into two patches to provide for device specific init in one patch with no effect on existing designs. Then add the pensando support into the next patch. Then the 4th patch is mmc hardware reset support which is unchanged. v9 changes: - No change to this patch but as some patches are deleted and this is a respin the three successive patches to sdhci-cadence.c are patches 12, 13, and 14 which do the following: 1. Add ability for Cadence specific design to have priv writel(). 2. Add Elba SoC support that requires its own priv writel() for byte-lane control . 3. Add support for mmc hardware reset. --- drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 6f2de54a5987..708d4297f241 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; bool enhanced_strobe; + void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; +static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + writel(val, reg); +} + static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u8 addr, u8 data) { @@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); tmp |= SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); if (ret) return ret; tmp &= ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 0, 10); @@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) @@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) */ for (i = 0; i < 2; i++) { tmp |= SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), @@ -386,6 +393,7 @@ static int sdhci_cdns_probe(struct platform_device *pdev) priv->nr_phy_params = nr_phy_params; priv->hrs_addr = host->ioaddr; priv->enhanced_strobe = false; + priv->priv_writel = cdns_writel; host->ioaddr += SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe;