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Ip=[20.160.56.82]; Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: DB8EUR05FT006.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB9935 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org dpmac1 defaults to a fixed link. However, it has an SFP cage, so we can determine more about the link (such as whether it's up/down) by describing it. The GPIOs are part of the "QIXIS" FPGA. For now, just model them as individual registers. Signed-off-by: Sean Anderson --- (no changes since v13) Changes in v13: - Split off SFP addition from serdes support .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 51 ++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 391c2b8afa81..9fb1960f1258 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -10,11 +10,27 @@ /dts-v1/; +#include + #include "fsl-ls1088a.dtsi" / { model = "LS1088A RDB Board"; compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; + + sfp_slot: sfp { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c>; + los-gpios = <&los_stat 5 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&los_stat 4 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&brdcfg9 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&dpmac1 { + managed = "in-band-status"; + pcs-handle = <&pcs1>; + sfp = <&sfp_slot>; }; &dpmac2 { @@ -170,6 +186,12 @@ rtc@51 { interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>; }; }; + + sfp_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; }; }; @@ -184,8 +206,31 @@ nand@0,0 { }; fpga: board-control@2,0 { - compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis", + "simple-bus"; reg = <0x2 0x0 0x0000100>; + ranges = <0x0 0x2 0x0 0x0000100>; + + los_stat: gpio-controller@1d { + #gpio-cells = <2>; + compatible = "fsl,fpga-qixis-los-stat", + "ni,169445-nand-gpio"; + reg = <0x1d 0x1>; + reg-names = "dat"; + gpio-controller; + no-output; + }; + + brdcfg9: gpio-controller@59 { + #gpio-cells = <2>; + compatible = "fsl,fpga-qixis-brdcfg9", + "ni,169445-nand-gpio"; + reg = <0x59 0x1>; + reg-names = "dat"; + gpio-controller; + }; }; }; @@ -202,6 +247,10 @@ &esdhc { status = "okay"; }; +&pcs_mdio1 { + status = "okay"; +}; + &pcs_mdio2 { status = "okay"; };