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Thu, 13 Apr 2023 16:06:59 +0000 Received: from DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::2226:eb03:a8c:a7e5]) by DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::2226:eb03:a8c:a7e5%2]) with mapi id 15.20.6298.030; Thu, 13 Apr 2023 16:06:59 +0000 From: Sean Anderson To: Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org Cc: Madalin Bucur , linux-arm-kernel@lists.infradead.org, Camelia Alexandra Groza , devicetree@vger.kernel.org, Rob Herring , linuxppc-dev@lists.ozlabs.org, Bagas Sanjaya , Krzysztof Kozlowski , Ioana Ciornei , Sean Anderson , Li Yang , Shawn Guo Subject: [PATCH v14 15/15] arm64: dts: ls1088ardb: Add serdes descriptions Date: Thu, 13 Apr 2023 12:06:07 -0400 Message-Id: <20230413160607.4128315-16-sean.anderson@seco.com> X-Mailer: git-send-email 2.35.1.1320.gc452695387.dirty In-Reply-To: <20230413160607.4128315-1-sean.anderson@seco.com> References: <20230413160607.4128315-1-sean.anderson@seco.com> X-ClientProxiedBy: BL1P221CA0007.NAMP221.PROD.OUTLOOK.COM (2603:10b6:208:2c5::33) To DB9PR03MB8847.eurprd03.prod.outlook.com (2603:10a6:10:3dd::13) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DB9PR03MB8847:EE_|DB9PR03MB8325:EE_|AM6EUR05FT065:EE_|VI1PR03MB6430:EE_ X-MS-Office365-Filtering-Correlation-Id: a43605ff-2560-4469-5a0a-08db3c39243b X-TrendMicro-CAS-OUT-LOOP-IDENTIFIER: 656f966764b7fb185830381c646b41a1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: AM6EUR05FT065.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR03MB6430 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds serdes support to the LS1088ARDB. I have tested the QSGMII ports as well as the two 10G ports. Linux hangs around when the serdes is initialized if the si5341 is enabled with the in-tree driver, so I have modeled it as a two fixed clocks instead. To enable serdes support, the DPC needs to set the macs to MAC_LINK_TYPE_BACKPLANE. All MACs using the same QSGMII should be converted at once. Additionally, in order to change interface types, the MC firmware must support DPAA2_MAC_FEATURE_PROTOCOL_CHANGE. Signed-off-by: Sean Anderson --- (no changes since v13) Changes in v13: - Split off interrupt and SFP changes into separate commits Changes in v10: - Move serdes bindings to SoC dtsi - Use "descriptions" instead of "bindings" - Don't use /clocks - Add missing gpio-controller properties Changes in v9: - Add fsl,unused-lanes-reserved to allow a gradual transition, depending on the mac link type. - Remove unused clocks - Fix some phy mode node names - phy-type -> fsl,phy Changes in v8: - Rename serdes phy handles like the LS1046A - Add SFP slot binding - Fix incorrect lane ordering (it's backwards on the LS1088A just like it is in the LS1046A). - Fix duplicated lane 2 (it should have been lane 3). - Fix incorrectly-documented value for XFI1. - Remove interrupt for aquantia phy. It never fired for whatever reason, preventing the link from coming up. - Add GPIOs for QIXIS FPGA. - Enable MAC1 PCS - Remove si5341 binding Changes in v4: - Convert to new bindings .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 9fb1960f1258..ede537b644e8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -18,6 +18,18 @@ / { model = "LS1088A RDB Board"; compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; + clk_100mhz: clock-100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk_156mhz: clock-156mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + sfp_slot: sfp { compatible = "sff,sfp"; i2c-bus = <&sfp_i2c>; @@ -27,16 +39,26 @@ sfp_slot: sfp { }; }; +&serdes1 { + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; + fsl,unused-lanes-reserved; + status = "okay"; +}; + &dpmac1 { managed = "in-band-status"; pcs-handle = <&pcs1>; + phys = <&serdes1_C>; sfp = <&sfp_slot>; }; &dpmac2 { phy-handle = <&mdio2_aquantia_phy>; phy-connection-type = "10gbase-r"; + managed = "in-band-status"; pcs-handle = <&pcs2>; + phys = <&serdes1_D>; }; &dpmac3 { @@ -44,6 +66,7 @@ &dpmac3 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_0>; + phys = <&serdes1_A>; }; &dpmac4 { @@ -51,6 +74,7 @@ &dpmac4 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_1>; + phys = <&serdes1_A>; }; &dpmac5 { @@ -58,6 +82,7 @@ &dpmac5 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_2>; + phys = <&serdes1_A>; }; &dpmac6 { @@ -65,6 +90,7 @@ &dpmac6 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_3>; + phys = <&serdes1_A>; }; &dpmac7 { @@ -72,6 +98,7 @@ &dpmac7 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_0>; + phys = <&serdes1_B>; }; &dpmac8 { @@ -79,6 +106,7 @@ &dpmac8 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_1>; + phys = <&serdes1_B>; }; &dpmac9 { @@ -86,6 +114,7 @@ &dpmac9 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_2>; + phys = <&serdes1_B>; }; &dpmac10 { @@ -93,6 +122,7 @@ &dpmac10 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_3>; + phys = <&serdes1_B>; }; &emdio1 {