From patchwork Sat Apr 15 10:40:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 673468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99B5CC7619A for ; Sat, 15 Apr 2023 10:41:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229773AbjDOKlT (ORCPT ); Sat, 15 Apr 2023 06:41:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229540AbjDOKlR (ORCPT ); Sat, 15 Apr 2023 06:41:17 -0400 Received: from mail-il1-x12b.google.com (mail-il1-x12b.google.com [IPv6:2607:f8b0:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F2D04C3F; Sat, 15 Apr 2023 03:41:16 -0700 (PDT) Received: by mail-il1-x12b.google.com with SMTP id e9e14a558f8ab-32a7770f7d1so13783095ab.1; Sat, 15 Apr 2023 03:41:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681555275; x=1684147275; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=NxV/r2dg6tmyFGrf7XbFu39RjdGZZ9Qw/qpOckRtFcs=; b=nkxVRMgX1GxubqUedgn9gXUJHy+brhU+3BcUFfjVgyCkoGudE9vSWr3Y8suNnwiEv+ W8yGBeGfODXBLYCs6nVn2KX4m+oD6yWq/F1eRJp3Z+aFjU608yiclFytafmdERH3CJJR HtMwgvVu1OTXrkiIiNzRBci8NMvJdEMUm8Oj5Vm31359sF/pA4PDYmJMIsd9Q8h1Y8Xk q+HUt00HV7vkK9y9UukZsBljW5DjBzm9uSDN7sChkNbjExgM9QLRAx2Hytcq1BZp8C/o iw2zx3nm8q2SPJVubnoX8TCVQCtB4H2vnS4TKmGvyjsAoFY9mfB+fRsHBMnwUpLQeHr3 baZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681555275; x=1684147275; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=NxV/r2dg6tmyFGrf7XbFu39RjdGZZ9Qw/qpOckRtFcs=; b=AeTVLMF1o+SQClNYYmvBvgWjb9dXzltjoNQppHOE2h2RkS1JDB7e0uZ12eNE3cIRU6 5oXcbltkiWStuaTfHvI7sfmm9xeaBo2pQRnFszoVbn4Ife2hDz46q51nTaH6LIi4lZwR W4xWB8ZTIT/8l01h5dgMO49uV8zMSrx8FE6NfIRXzv5SQqYcZ/xX7E3XkpBEA5N5Qv7l HTqJNv4slHKToAmcnN8sbVFQbz35InNlTBB5dUTjBU/iBg64rVXsEgRU3wqRhnHPzbeg AhXpVOjgO+QgdGh5ukmj9OkS16fpsG/dlFKtZIFIgFDzVdMbqnG4PesmpauoV4HTVGOM viQQ== X-Gm-Message-State: AAQBX9eqgNSktpfTVyRM1ItAm+6IQwaEUgrEYV7m0x7csOugrliEH6+r Ijlwo4tS+uBxNvCGak4tc5E= X-Google-Smtp-Source: AKy350be9XGQbEpTAMxfp/yDs4zbKCqaElyWQiPWqA6tPdcVQdgTQGeHdLNOwe+rg1tq3rDX2lHvrA== X-Received: by 2002:a05:6e02:526:b0:328:edf8:be71 with SMTP id h6-20020a056e02052600b00328edf8be71mr5849677ils.0.1681555275334; Sat, 15 Apr 2023 03:41:15 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:40bb:6fe6:ddbc:cc9a]) by smtp.gmail.com with ESMTPSA id bp11-20020a056638440b00b0040b38102b79sm246536jab.82.2023.04.15.03.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Apr 2023 03:41:14 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: m.szyprowski@samsung.com, marex@denx.de, aford@beaconembedded.com, Adam Ford , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Inki Dae , Jagan Teki , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] drm: bridge: samsung-dsim: Support multi-lane calculations Date: Sat, 15 Apr 2023 05:40:58 -0500 Message-Id: <20230415104104.5537-1-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If there is more than one lane, the HFP, HBP, and HSA is calculated in bytes/pixel, then they are divided amongst the different lanes with some additional overhead. This is necessary to achieve higher resolutions while keeping the pixel clocks lower as the number of lanes increase. Signed-off-by: Adam Ford --- drivers/gpu/drm/bridge/samsung-dsim.c | 40 +++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index e0a402a85787..1ccbad4ea577 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -215,6 +215,7 @@ #define DSI_RX_FIFO_SIZE 256 #define DSI_XFER_TIMEOUT_MS 100 #define DSI_RX_FIFO_EMPTY 0x30800002 +#define DSI_HSYNC_PKT_OVERHEAD 6 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" @@ -879,13 +880,40 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); - reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) - | DSIM_MAIN_HBP(m->htotal - m->hsync_end); - samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); + /* + * If there is more than one lane, the HFP, HBP, and HSA + * is calculated in bytes/pixel, then they are divided + * amongst the different lanes with some additional + * overhead correction + */ + if (dsi->lanes > 1) { + u32 hfp, hbp, hsa; + int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format) / 8; + + hfp = ((m->hsync_start - m->hdisplay) * bpp) / dsi->lanes; + hfp -= (hfp > DSI_HSYNC_PKT_OVERHEAD) ? DSI_HSYNC_PKT_OVERHEAD : 0; + + hbp = ((m->htotal - m->hsync_end) * bpp) / dsi->lanes; + hbp -= (hbp > DSI_HSYNC_PKT_OVERHEAD) ? DSI_HSYNC_PKT_OVERHEAD : 0; - reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) - | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); - samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); + hsa = ((m->hsync_end - m->hsync_start) * bpp) / dsi->lanes; + hsa -= (hsa > DSI_HSYNC_PKT_OVERHEAD) ? DSI_HSYNC_PKT_OVERHEAD : 0; + + reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); + samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); + + reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) + | DSIM_MAIN_HSA(hsa); + samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); + } else { + reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) + | DSIM_MAIN_HBP(m->htotal - m->hsync_end); + samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); + + reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) + | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); + samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); + } } reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);