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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/gate-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock which can gate its output
+
+maintainers:
+ - David Yang <mmyangfl@gmail.com>
+
+description: |
+ Clock which can gate its output, by toggling one bit in a register. Such
+ register may also control other clocks or reset requests.
+
+ The registers map is retrieved from the parental dt-node. So the clock node
+ should be represented as a sub-node of a "clock-controller" node.
+
+ See also: Documentation/devicetree/bindings/clock/simple-clock-controller.yaml
+
+properties:
+ compatible:
+ const: gate-clock
+
+ '#clock-cells':
+ const: 0
+
+ clocks:
+ maxItems: 1
+ description: Parent clock.
+
+ offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Offset in the register map for the control register (in bytes).
+
+ bits:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Bit index which controls the output.
+
+ clock-output-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#clock-cells'
+ - offset
+ - bits
+
+additionalProperties: false
+
+examples:
+ - |
+ clock {
+ compatible = "gate-clock";
+ #clock-cells = <0>;
+ offset = <0xcc>;
+ bits = <3>;
+ clock-output-names = "my-clk";
+ };
Add DT bindings documentation for gate clock, which can gate its output. Signed-off-by: David Yang <mmyangfl@gmail.com> --- .../devicetree/bindings/clock/gate-clock.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/gate-clock.yaml