From patchwork Mon Apr 17 09:26:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 673995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CCA7C77B76 for ; Mon, 17 Apr 2023 09:27:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229655AbjDQJ10 (ORCPT ); Mon, 17 Apr 2023 05:27:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229515AbjDQJ1U (ORCPT ); Mon, 17 Apr 2023 05:27:20 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 691B940F3; Mon, 17 Apr 2023 02:27:11 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id c9so23510696ejz.1; Mon, 17 Apr 2023 02:27:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681723630; x=1684315630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fadIVQZBpq46XVVpnX4ew17nOLJ18aM1wvmfilOrUDc=; b=psQTvOwN7Im7UB8QEqR2OSmFumZOFwO6TfC7CGzCAdqk7edTq9n3bBGXaoFaeDrOnq 2wFEn2W/7f2ZdIIE9H3kNRoKffbD/ADS9E4RD5qMWcjFYDIVn4TDga04IfHew+3SIkbu 0/8YJXw3h91Mn6e1C690x8WkRkdDFiyplTC7/09g5JDMBs/pf+BA9Pgl/D8c8Y0zTP+e dZKMuXH3oMHdnjXah6c7hv0yGPE2NHN93OJla4VTECgKG9hzck9ve6ZDTJqqErH10mLF EgF0EetFr3vu+fP86r9QLq5hGlSBTOXplsltx6aZjpuw+OsizK/psmfVxBRGHrDeKgta HfKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681723630; x=1684315630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fadIVQZBpq46XVVpnX4ew17nOLJ18aM1wvmfilOrUDc=; b=IjIq25ieYW0tibpQiZoqgTRVWfpm92rkBwMZWXYICW95VcaYHfsLMJqUDuw2MkVNUA s9fOWfGCUFhmA6wrbwfiyY6pXCvuNTdlDUGCq9p8OdnRiuNdM9C3QgOVVXqvzG4RE225 A2nNThDR9+1K4KAx72e8H70n8//GEUv7/i3MB3EIygbdeMS+/3kSRs1ZqhgmxnzAYx/u S9iml2B1cvo4DJHjDDes8hGx2vBGUKblc7iwBMmq8V27wlo6qbv81n8b+X4IQQqWgja8 Hz7jr4LF51B5BpjFW8zX7m0QptvJXF9CuDJXlBwZDMldmL5MaJpkzBKS6YodMlNipSAB /ysw== X-Gm-Message-State: AAQBX9fHRfandT/uh+SIL0UoX7901Sw6kkGrJ/x1joIX1xlVhR189Whx Go1NF2ZYknhoMTX+cIH8d7Y= X-Google-Smtp-Source: AKy350awxorBAKdXhAo3Z/z2Yp8EU/GCSvHG4r9Ik0g7z6c9I+WLLYKUpyzkR7qfK0ZCMmbd9CUb4Q== X-Received: by 2002:a17:906:6d0f:b0:935:20d8:c3c with SMTP id m15-20020a1709066d0f00b0093520d80c3cmr6848788ejr.61.1681723629914; Mon, 17 Apr 2023 02:27:09 -0700 (PDT) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id p20-20020a170906615400b0094aa087578csm6398596ejl.171.2023.04.17.02.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 02:27:09 -0700 (PDT) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, Rick Wertenbroek , Damien Le Moal , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Heiko Stuebner , Corentin Labbe , Brian Norris , Caleb Connolly , Johan Jonker , Judy Hsiao , Hugh Cole-Baker , Arnaud Ferraris , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 05/11] arm64: dts: rockchip: Add dtsi entry for RK3399 PCIe endpoint core Date: Mon, 17 Apr 2023 11:26:23 +0200 Message-Id: <20230417092631.347976-6-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230417092631.347976-1-rick.wertenbroek@gmail.com> References: <20230417092631.347976-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dtsi entry for RK3399 PCIe endpoint core in the device tree. The status is "disabled" by default, so it will not be loaded unless explicitly chosen to. The RK3399 PCIe endpoit core should be enabled with the RK3399 PCIe root complex disabled because the RK3399 PCIe controller can only work one mode at the time, either in "root complex" mode or in "endpoint" mode. Signed-off-by: Rick Wertenbroek Tested-by: Damien Le Moal --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 928948e7c7bb..9da0b6d77c8d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -265,6 +265,33 @@ pcie0_intc: interrupt-controller { }; }; + pcie0_ep: pcie-ep@f8000000 { + compatible = "rockchip,rk3399-pcie-ep"; + reg = <0x0 0xfd000000 0x0 0x1000000>, + <0x0 0xfa000000 0x0 0x2000000>; + reg-names = "apb-base", "mem-base"; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + max-functions = /bits/ 8 <8>; + num-lanes = <4>; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, + <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + phys = <&pcie_phy 0>, <&pcie_phy 1>, + <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", + "pcie-phy-2", "pcie-phy-3"; + rockchip,max-outbound-regions = <32>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + status = "disabled"; + }; + gmac: ethernet@fe300000 { compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>;