From patchwork Tue Apr 18 12:06:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 675348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2267C77B75 for ; Tue, 18 Apr 2023 12:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231626AbjDRMI5 (ORCPT ); Tue, 18 Apr 2023 08:08:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231536AbjDRMIg (ORCPT ); Tue, 18 Apr 2023 08:08:36 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20192B75A; Tue, 18 Apr 2023 05:06:39 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id C125E660320E; Tue, 18 Apr 2023 13:06:37 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1681819598; bh=TQcB5X4iZIViJGyWOJ/d+KxnISkUh4MekvbHwYmTdXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oFDWMnpZdoO3UisFSu/SMZB0jfMFuAlpH18h+bsJa8M+zrtPMfDOCYA6Whd8lcZTY rRPbnp2pBY1oFfAtEi52kGJnz3moIECfOzNLDViBcUfevkKAIQCy1TLUYxw6SGwsnq IFsMYYrSIy50dnRLUZoGxhbcWukNgm3/mDGe+lkKVlrWlgeo0i1asK6Se+NHdOYkMz QG8aT1X/GC36M9hz+E+s0qmIVwt7pdecBa2NACIskLnH67ITi1RcsqkLcDPwxLmZCv KLV8M13KYk/fo0TLTrHz9kbBmzYQ9UvItdZTtYnb0OkoFs9wv1sYjyqGDyclq9LF5b 2jlEX/8tWz6SQ== From: Cristian Ciocaltea To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sebastian Reichel , Sugar Zhang , Shreeya Patel , Kever Yang , Johan Jonker Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 3/3] arm64: dts: rockchip: Add rk3588 timer Date: Tue, 18 Apr 2023 15:06:24 +0300 Message-Id: <20230418120624.284551-4-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230418120624.284551-1-cristian.ciocaltea@collabora.com> References: <20230418120624.284551-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT node for Rockchip RK3588/RK3588S SoC timer. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 657c019d27fa..767084a1ec43 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1400,6 +1400,14 @@ i2c5: i2c@fead0000 { status = "disabled"; }; + timer0: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + wdt: watchdog@feaf0000 { compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; reg = <0x0 0xfeaf0000 0x0 0x100>;