From patchwork Mon Apr 24 11:19:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 676692 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B01EC77B61 for ; Mon, 24 Apr 2023 11:20:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231481AbjDXLUJ (ORCPT ); Mon, 24 Apr 2023 07:20:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231510AbjDXLUI (ORCPT ); Mon, 24 Apr 2023 07:20:08 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B0E230ED; Mon, 24 Apr 2023 04:20:04 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33OBJuB7078126; Mon, 24 Apr 2023 06:19:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1682335196; bh=znsw8gLLmzY1kmekM/w5JfjECm+1AZE6YR765Rk8j00=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Vk/CiJHukJTAWShImLPqC3oI2WIWkhxfTZLU8TChDkmYIneXrYiCei4cb2qcL+pq8 FLi6gJcJNPC9fPKJ76DqbDO+yzIfZAXn/hz0ZiRFq0uppUwn5/91QDK6+Opg9tur0n mOC07pQOBOhSYbWuxfgGLF0WPdqTkFy8L2GtcvAY= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33OBJuXE038976 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 24 Apr 2023 06:19:56 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 24 Apr 2023 06:19:56 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 24 Apr 2023 06:19:56 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33OBJjiY100294; Mon, 24 Apr 2023 06:19:53 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [RFC PATCH 2/2] arm64: dts: ti: k3-am62a7: Add overlay for second CPSW3G Port Date: Mon, 24 Apr 2023 16:49:45 +0530 Message-ID: <20230424111945.3865240-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424111945.3865240-1-s-vadapalli@ti.com> References: <20230424111945.3865240-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SK-Ethernet-DC01 Add-On Ethernet Card for AM62A7-SK board supports RGMII mode. Add overlay to enable the second CPSW3G port in RGMII-RXID mode with the Add-On Ethernet Card. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/Makefile | 2 + .../dts/ti/k3-am62a7-sk-ethernet-dc01.dtso | 61 +++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c83c9d772b81..62d4c3956495 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-ethernet-dc01.dtbo # Boards with AM64x SoC dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb @@ -48,4 +49,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb # Enable support for device-tree overlays +DTC_FLAGS_k3-am62a7-sk += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso b/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso new file mode 100644 index 000000000000..c518cd32f697 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for second CPSW3G port in RGMII mode using SK-ETHERNET-DC01 + * Add-On Daughtercard with AM62A7-SK. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2"; + }; +}; + +&cpsw3g { + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + #address-cells = <1>; + #size-cells = <0>; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_pmx0 { + main_rgmii2_pins_default: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0184, PIN_INPUT, 0) /* (AA21) RGMII2_RD0 */ + AM62AX_IOPAD(0x0188, PIN_INPUT, 0) /* (Y20) RGMII2_RD1 */ + AM62AX_IOPAD(0x018c, PIN_INPUT, 0) /* (AB21) RGMII2_RD2 */ + AM62AX_IOPAD(0x0190, PIN_INPUT, 0) /* (AB20) RGMII2_RD3 */ + AM62AX_IOPAD(0x0180, PIN_INPUT, 0) /* (AA20) RGMII2_RXC */ + AM62AX_IOPAD(0x017c, PIN_INPUT, 0) /* (W18) RGMII2_RX_CTL */ + AM62AX_IOPAD(0x016c, PIN_INPUT, 0) /* (AA19) RGMII2_TD0 */ + AM62AX_IOPAD(0x0170, PIN_INPUT, 0) /* (Y18) RGMII2_TD1 */ + AM62AX_IOPAD(0x0174, PIN_INPUT, 0) /* (AA18) RGMII2_TD2 */ + AM62AX_IOPAD(0x0178, PIN_INPUT, 0) /* (W17) RGMII2_TD3 */ + AM62AX_IOPAD(0x0168, PIN_INPUT, 0) /* (AB19) RGMII2_TXC */ + AM62AX_IOPAD(0x0164, PIN_INPUT, 0) /* (Y19) RGMII2_TX_CTL */ + >; + }; +};