From patchwork Mon May 8 18:16:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 679982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12931C77B75 for ; Mon, 8 May 2023 18:17:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233007AbjEHSRU (ORCPT ); Mon, 8 May 2023 14:17:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233074AbjEHSRT (ORCPT ); Mon, 8 May 2023 14:17:19 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E873F5FC7 for ; Mon, 8 May 2023 11:17:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5180A62F14 for ; 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a=openpgp-sha256; l=2933; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=sxz5UhIOaJj8Re9+hSvtSwbaV+pJMl6xzcAp79D9KJ0=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNmWBZjpFz00vJS05+L9L+f2fzB2CqnuOxv4vyjCY1 aDQqX6io5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABM5JcXIsDaoQu7ndSPHiFVZ b6r+XVDUX7+QO+WEwN/4JVafG774vWT4n/X1LGvk2k8PHu2w26F8MObA3czOT/KLMu2ezbrw/db +2UwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 42 ++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 104504352e99..53efb5e03c64 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -21,7 +21,11 @@ cpu0: cpu@0 { i-cache-sets = <128>; i-cache-size = <16384>; reg = <0>; - riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; @@ -47,7 +51,14 @@ cpu1: cpu@1 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <1>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -75,7 +86,14 @@ cpu2: cpu@2 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <2>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -103,7 +121,14 @@ cpu3: cpu@3 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <3>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -131,7 +156,14 @@ cpu4: cpu@4 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <4>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>;