From patchwork Fri May 12 02:20:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 681389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31E12C7EE2F for ; Fri, 12 May 2023 02:22:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239797AbjELCW1 convert rfc822-to-8bit (ORCPT ); Thu, 11 May 2023 22:22:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239780AbjELCWW (ORCPT ); Thu, 11 May 2023 22:22:22 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B90365BA5; Thu, 11 May 2023 19:22:20 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 00D1E817A; Fri, 12 May 2023 10:22:14 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 12 May 2023 10:22:13 +0800 Received: from localhost.localdomain (113.72.146.187) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 12 May 2023 10:22:12 +0800 From: Xingyu Wu To: , , "Michael Turquette" , Stephen Boyd , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , "Emil Renner Berthing" CC: Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Xingyu Wu , William Qiu , , Subject: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Date: Fri, 12 May 2023 10:20:30 +0800 Message-ID: <20230512022036.97987-2-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230512022036.97987-1-xingyu.wu@starfivetech.com> References: <20230512022036.97987-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.146.187] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xingyu Wu --- .../bindings/clock/starfive,jh7110-pll.yaml | 46 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh7110-crg.h | 6 +++ 2 files changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml new file mode 100644 index 000000000000..8aa8c7b8e42f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PLL Clock Generator + +description: + This PLL are high speed, low jitter frequency synthesizers in JH7110. + Each PLL clocks work in integer mode or fraction mode by some dividers, + and the configuration registers and dividers are set in several syscon + registers. So pll node should be a child of SYS-SYSCON node. + The formula for calculating frequency is that, + Fvco = Fref * (NI + NF) / M / Q1 + +maintainers: + - Xingyu Wu + +properties: + compatible: + const: starfive,jh7110-pll + + clocks: + maxItems: 1 + description: Main Oscillator (24 MHz) + + '#clock-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + pll-clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index 06257bfd9ac1..086a6ddcf380 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -6,6 +6,12 @@ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +/* PLL clocks */ +#define JH7110_CLK_PLL0_OUT 0 +#define JH7110_CLK_PLL1_OUT 1 +#define JH7110_CLK_PLL2_OUT 2 +#define JH7110_PLLCLK_END 3 + /* SYSCRG clocks */ #define JH7110_SYSCLK_CPU_ROOT 0 #define JH7110_SYSCLK_CPU_CORE 1