From patchwork Tue May 16 06:47:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Tu X-Patchwork-Id: 682735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67E6AC77B75 for ; Tue, 16 May 2023 06:49:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230379AbjEPGtr (ORCPT ); Tue, 16 May 2023 02:49:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230346AbjEPGtc (ORCPT ); Tue, 16 May 2023 02:49:32 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCB6F3A91; Mon, 15 May 2023 23:48:47 -0700 (PDT) Received: from droid06.amlogic.com (10.18.11.248) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Tue, 16 May 2023 14:48:37 +0800 From: Yu Tu To: , , , , , Rob Herring , "Neil Armstrong" , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , "Krzysztof Kozlowski" , Conor Dooley , Martin Blumenstingl CC: , , Yu Tu Subject: [PATCH V8 RESEND 1/4] dt-bindings: clock: document Amlogic S4 SoC PLL clock controller Date: Tue, 16 May 2023 14:47:33 +0800 Message-ID: <20230516064736.10270-2-yu.tu@amlogic.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20230516064736.10270-1-yu.tu@amlogic.com> References: <20230516064736.10270-1-yu.tu@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.248] Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the S4 PLL clock controller dt-bindings in the s4 SoC family. Signed-off-by: Yu Tu --- .../bindings/clock/amlogic,s4-pll-clkc.yaml | 50 +++++++++++++++++++ MAINTAINERS | 1 + .../dt-bindings/clock/amlogic,s4-pll-clkc.h | 30 +++++++++++ 3 files changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,s4-pll-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml new file mode 100644 index 000000000000..242cceb5033a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic S serials PLL Clock Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Yu Tu + +properties: + compatible: + const: amlogic,s4-pll-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clkc_pll: clock-controller@fe008000 { + compatible = "amlogic,s4-pll-clkc"; + reg = <0xfe008000 0x1e8>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e..09422aa49f61 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1888,6 +1888,7 @@ L: linux-amlogic@lists.infradead.org S: Maintained F: Documentation/devicetree/bindings/clock/amlogic* F: drivers/clk/meson/ +F: include/dt-bindings/clock/amlogic* F: include/dt-bindings/clock/gxbb* F: include/dt-bindings/clock/meson* diff --git a/include/dt-bindings/clock/amlogic,s4-pll-clkc.h b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h new file mode 100644 index 000000000000..1dcdedb1a6dd --- /dev/null +++ b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Yu Tu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H + +/* + * CLKID index values + */ + +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 3 +#define CLKID_FCLK_DIV3 5 +#define CLKID_FCLK_DIV4 7 +#define CLKID_FCLK_DIV5 9 +#define CLKID_FCLK_DIV7 11 +#define CLKID_FCLK_DIV2P5 13 +#define CLKID_GP0_PLL 15 +#define CLKID_HIFI_PLL 17 +#define CLKID_HDMI_PLL 20 +#define CLKID_MPLL_50M 22 +#define CLKID_MPLL0 25 +#define CLKID_MPLL1 27 +#define CLKID_MPLL2 29 +#define CLKID_MPLL3 31 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */