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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id 9-20020a05651c040900b002a8c271de33sm1919259lja.67.2023.05.17.09.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 09:40:49 -0700 (PDT) From: Konrad Dybcio Date: Wed, 17 May 2023 18:40:39 +0200 Subject: [PATCH 2/4] clk: qcom: rcg2: Make hw_clk_ctrl toggleable MIME-Version: 1.0 Message-Id: <20230517-topic-waipio-gpucc-v1-2-4f40e282af1d@linaro.org> References: <20230517-topic-waipio-gpucc-v1-0-4f40e282af1d@linaro.org> In-Reply-To: <20230517-topic-waipio-gpucc-v1-0-4f40e282af1d@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: Marijn Suijten , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684341644; l=1689; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=fnX8Gs7THnPKyxc7XYOaJzSXtKdHLn/shBY+gLa1OAc=; b=dc7FDYnfPDVDqiSyXx2sBVWzWIEGK2mW+pKm3QRUvO8ubVk5bfUJ7nDe0HxUNk6RCH6W5Kwgo 5HC3owtkZg7Dw/0EFcRcNNhwp7/Ei6prAIfkiumFuISDWhw/Cw+Mazg X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Certain SoCs use the HW_CLK_CTRL feature on some of the clocks they host. This allows the clocks to be turned on automatically when a downstream branch tries to change rate or config. Make it togglable so that we can utilize this. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-rcg.h | 2 ++ drivers/clk/qcom/clk-rcg2.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 01581f4d2c39..e6d84c8c7989 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -141,6 +141,7 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @clkr: regmap clock handle * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG * @parked_cfg: cached value of the CFG register for parked RCGs + * @hw_clk_ctrl: whether to enable hardware clock control */ struct clk_rcg2 { u32 cmd_rcgr; @@ -152,6 +153,7 @@ struct clk_rcg2 { struct clk_regmap clkr; u8 cfg_off; u32 parked_cfg; + bool hw_clk_ctrl; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 76551534f10d..e22baf3a7112 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -325,6 +325,8 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m != f->n)) cfg |= CFG_MODE_DUAL_EDGE; + if (rcg->hw_clk_ctrl) + cfg |= CFG_HW_CLK_CTRL_MASK; *_cfg &= ~mask; *_cfg |= cfg;