From patchwork Fri May 19 21:36:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 684384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26D52C77B7A for ; Fri, 19 May 2023 21:38:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231401AbjESViK (ORCPT ); Fri, 19 May 2023 17:38:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231739AbjESViI (ORCPT ); Fri, 19 May 2023 17:38:08 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 197D1E6B; Fri, 19 May 2023 14:38:00 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34JLOLAI031661; Fri, 19 May 2023 21:37:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=8kMd9I9nK+eyP/i8tgPXVXTLTP0GC4mDhJJCZnDImmM=; b=FUrariuSJ+L+POCeeDy7+NvpAeOu07nrxQWufeK7xQHRM2CtK2RwtDJlvwO81zT9oQCU bkPDFVOy32FT7qbyURUPxNjaCBlQe+YhKEswYesNcH7N5j4LA7YLjWQLAdj792GDZnPk OKeU0ENknr8NktPR5LwAo5yJdqrY3bQiOqDQiSufM8kC8ox3ruBP3SSdFqcr/w6TQ6fE HxPC12x+F30Eb3AMRqoFD6Lwfoq6/Wl0pjpyvhqdthB9DnrH0deFHt736BPSreK00LVQ WQHBfYPDTiWuH9kPgUc+VJiWW6pgk1KGnIcith0Je0dsCYGW/iOxiD4+xFkKST6hUds0 Cg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qp4nt9xhu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 19 May 2023 21:37:56 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34JLbt5S015585 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 19 May 2023 21:37:55 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 19 May 2023 14:37:50 -0700 From: Jagadeesh Kona To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Konrad Dybcio , , , , , Satya Priya Kakitapalli , Taniya Das , "Jagadeesh Kona" Subject: [PATCH 3/3] arm64: dts: qcom: sm8550: Add graphics clock controller Date: Sat, 20 May 2023 03:06:56 +0530 Message-ID: <20230519213656.26089-4-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230519213656.26089-1-quic_jkona@quicinc.com> References: <20230519213656.26089-1-quic_jkona@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: FEf5leIXnT-YV_RJlasKAnTvBAM69xY5 X-Proofpoint-GUID: FEf5leIXnT-YV_RJlasKAnTvBAM69xY5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-19_16,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 phishscore=0 spamscore=0 impostorscore=0 bulkscore=0 malwarescore=0 mlxscore=0 mlxlogscore=983 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305190187 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device node for graphics clock controller on Qualcomm SM8550 platform. Signed-off-by: Jagadeesh Kona Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index e67e7c69dae6..5258b057f51c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -1963,6 +1964,17 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8550-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8550-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>;