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Wed, 24 May 2023 19:20:56 +0000 From: Shenwei Wang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer Cc: Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Shenwei Wang Subject: [PATCH] arm64: dts: imx8-ss-dma: assign default clock rate for lpuarts Date: Wed, 24 May 2023 14:20:42 -0500 Message-Id: <20230524192042.133755-1-shenwei.wang@nxp.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: SJ0PR13CA0233.namprd13.prod.outlook.com (2603:10b6:a03:2c1::28) To AS8PR04MB9176.eurprd04.prod.outlook.com (2603:10a6:20b:44b::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB9176:EE_|DBBPR04MB7737:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b0fee9d-f13b-406e-1151-08db5c8bffa3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RsTj/E9r4e8UsfbpSQl7nnoNZUjnBjgETCqFEpjRG2dOO5XzgnAtYaXkNGIogZTmTpynW/BR9wv96JzTl6+fp/rVcUfUlwy1oQRlzG0Yto7OtCKUV/eB+rTE/Rj6NTtZ4udNEd6HfbkM/GzJY52fgMGB382BQPBjhe3JrZfZoyJMnReXM7Tcj9Cbn5Wt/BRxzyv227NQFTIcKFdGHX0Z/jbT5o7mE3flA8NukweWWi7K9DfqZvo5umLv44LkpHYPH1wtpAoUI9mxbRDR44/PCUYKx3X9f2NQYDTq9F95qtjcoeblm61c/nJ1WKmxhBWnSWNK/sHjpEyuh91BwsZJav2Ge93BrPYym4+9xpNVNbSeTIPBmVaAUeJnR5Xg1DyY9ZnTFOQCRXb/gUjCJpASIjHLclJ9weZfbODX9S9rtZtID3rkhp9L5QeNUMpsO+r4rqr2mSYytnsqkDZ4lQK2yPqorBEYdP797HADMMPY/FUdaXmok9AWV06z4V/3Na2tfmPWgYmmq+1/JXLWYlQcDLrlmBrcfi+yck2X+Vcg81MTHCioQdMIL/103H1ruDqmrqzR9gaTqjoM/8Kkvm1UpiD5GkIoWgWvJmC/3EYPBSC6ZWz3DNR/VI9ka7dQ9Q8W X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Without these properties, the default clock rate used would be 0, which can cause the UART ports to fail when open. Signed-off-by: Shenwei Wang --- arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index 2dce8f2ee3ea..adb98a72bdfd 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -90,6 +90,8 @@ lpuart0: serial@5a060000 { clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, <&uart0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_0>; status = "disabled"; }; @@ -100,6 +102,8 @@ lpuart1: serial@5a070000 { clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, <&uart1_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_1>; status = "disabled"; }; @@ -110,6 +114,8 @@ lpuart2: serial@5a080000 { clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, <&uart2_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_2>; status = "disabled"; }; @@ -120,6 +126,8 @@ lpuart3: serial@5a090000 { clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, <&uart3_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_3>; status = "disabled"; };