From patchwork Thu May 25 12:55:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 685735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C475C77B7A for ; Thu, 25 May 2023 12:57:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241130AbjEYM5S (ORCPT ); Thu, 25 May 2023 08:57:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233615AbjEYM5R (ORCPT ); Thu, 25 May 2023 08:57:17 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A017D1A6; Thu, 25 May 2023 05:57:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685019423; x=1716555423; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UikTxPTMS4kWoru+c9xlmXkh9gf6wCiMAK/SmT/FiLU=; b=oOaZZSToF8rFTADuFnWLFkVyTH8G/hRjC83vHPpYZ6JmlIpquS20JqQh Rp85IKz4Llyz9t9xXFAqkYvM+cG45N9465y7b501ZD4CSHyjmhtEgyHCf hRwyHJXDzIsusc7vXXidtf9K0kAwLFXqdgAMROFbcpjnWxRU206cdW5aX r70gqFKpLK1srNX06H12Y1PxH1iRNHHHj0abgRHOb6Zfexlor5J2NO0wS 2nRYHWtKTsXfmstbZ1F3taJ1VV9ZQrN7L0yqbVtQYeCGCq/plA8cH2sTj 0xv7zxYpLRB3MNvbS5SfShOy1Ccbqb46aD3GGGP2Sc3lsLmyyluQO/W16 A==; X-IronPort-AV: E=Sophos;i="6.00,191,1681196400"; d="scan'208";a="217255331" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 May 2023 05:56:58 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 25 May 2023 05:56:56 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 25 May 2023 05:56:50 -0700 From: Claudiu Beznea To: , , , , , , , , , CC: , , , , "Claudiu Beznea" Subject: [PATCH 1/5] dt-bindings: timer: atmel,at91sam9260-pit: convert to yaml Date: Thu, 25 May 2023 15:55:58 +0300 Message-ID: <20230525125602.640855-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525125602.640855-1-claudiu.beznea@microchip.com> References: <20230525125602.640855-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Atmel PIT to YAML. Along with it clock binding has been added as the driver enables it to ensure proper hardware functionality. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/arm/atmel-sysregs.txt | 6 --- .../bindings/timer/atmel,at91sam9260-pit.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 67a66bf74895..7024839c5da2 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -4,12 +4,6 @@ Chipid required properties: - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" - reg : Should contain registers location and length -PIT Timer required properties: -- compatible: Should be "atmel,at91sam9260-pit" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the PIT which is the IRQ line - shared across all System Controller members. - PIT64B Timer required properties: - compatible: Should be "microchip,sam9x60-pit64b" - reg: Should contain registers location and length diff --git a/Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml b/Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml new file mode 100644 index 000000000000..f304cd68acd5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/atmel,at91sam9260-pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Periodic Interval Timer (PIT) + +maintainers: + - Claudiu Beznea + +description: + Atmel periodic interval timer provides the operating system’s scheduler + interrupt. It is designed to offer maximum accuracy and efficient management, + even for systems with long response time. + +properties: + compatible: + const: atmel,at91sam9260-pit + + reg: + maxItems: 1 + + interrupts: + description: + Contain interrupt for the PIT which is the IRQ line shared across all + System Controller members. + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + + pit: timer@fffffe40 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; +...