From patchwork Thu May 25 12:56:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 685733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D9F0C7EE2D for ; Thu, 25 May 2023 12:58:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241226AbjEYM6A (ORCPT ); Thu, 25 May 2023 08:58:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241203AbjEYM5t (ORCPT ); Thu, 25 May 2023 08:57:49 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59770E4F; Thu, 25 May 2023 05:57:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685019443; x=1716555443; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zXWmcNfVj5r4m70YB2L1aMH8putZ8+9SRme+s9zUBg0=; b=MjSKShLfengFMkXzkLObgktrXQd1RK7udzH5XF6wubeO0ov82Uwe/ZG9 QnL9l3GmX5r89ae+m922Br9nxxsQxsodw/C++sQAIHxSbD7j/mWgNGMJ0 gP5aIavmIsoGslYCmcPdxRrllWybz1F+URLBuYEJu6ShQFiNWWEy/+U/A dRXELbIAAL7s9jacemTtpAsiwgnn/MBkjgcx+5N+wl08fJYK6aKw7/v1v qdIR4eP5pYxiSbrQK/EK5Y8qIA1v8le+qXosc40m5OWpqK4E9oipCVKUL j5zUOjl7G+ftsqJtlMzey587z2g7Rra4U1WgOO90xmBP5nM6tu5vKjnNG Q==; X-IronPort-AV: E=Sophos;i="6.00,191,1681196400"; d="scan'208";a="215446720" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 May 2023 05:57:23 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 25 May 2023 05:57:21 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 25 May 2023 05:57:17 -0700 From: Claudiu Beznea To: , , , , , , , , , CC: , , , , "Claudiu Beznea" Subject: [PATCH 5/5] dt-bindings: timer: atmel,at91rm9200-st: convert to yaml Date: Thu, 25 May 2023 15:56:02 +0300 Message-ID: <20230525125602.640855-6-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525125602.640855-1-claudiu.beznea@microchip.com> References: <20230525125602.640855-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Atmel system timer to YAML. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/arm/atmel-sysregs.txt | 9 --- .../bindings/timer/atmel,at91rm9200-st.yaml | 66 +++++++++++++++++++ 2 files changed, 66 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 54d3f586403e..68c0eacb01ac 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -4,15 +4,6 @@ Chipid required properties: - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" - reg : Should contain registers location and length -System Timer (ST) required properties: -- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the ST which is the IRQ line - shared across all System Controller members. -- clocks: phandle to input clock. -Its subnodes can be: -- watchdog: compatible should be "atmel,at91rm9200-wdt" - RAMC SDRAM/DDR Controller required properties: - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" "atmel,at91sam9260-sdramc", diff --git a/Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml b/Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml new file mode 100644 index 000000000000..08ee459d9fa3 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/atmel,at91rm9200-st.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel System Timer (ST) + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: + Atmel system timer integrates a period interval timer, a watchdog timer and a + real-time timer. + +properties: + compatible: + oneOf: + - items: + - const: atmel,at91rm9200-st + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + description: + Contain interrupt for the ST which is the IRQ line shared across all + system controller members. + maxItems: 1 + + clocks: + maxItems: 1 + + watchdog: + $ref: ../watchdog/atmel,at91rm9200-wdt.yaml + description: + Child node describing watchdog. + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + + st: timer@fffffd00 { + compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; + reg = <0xfffffd00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + + watchdog { + compatible = "atmel,at91rm9200-wdt"; + }; + }; + +...