| Message ID | 20230526070421.25406-5-quic_kathirav@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/4] dt-bindings: nvmem: qfprom: add compatible for few IPQ SoCs | expand |
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 1a2c813ffd43..715fe51ff567 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -117,6 +117,13 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + qfprom: efuse@a4000 { + compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x5a1>; + #address-cells = <1>; + #size-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq9574-tlmm"; reg = <0x01000000 0x300000>;
IPQ9574 has efuse region to determine the various HW quirks. Lets add the initial support and the individual fuses will be added as they are required. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)