From patchwork Thu Jun 1 15:26:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 316BEC7EE32 for ; Thu, 1 Jun 2023 15:26:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234787AbjFAP06 (ORCPT ); Thu, 1 Jun 2023 11:26:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234540AbjFAP0w (ORCPT ); Thu, 1 Jun 2023 11:26:52 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CB7E196; Thu, 1 Jun 2023 08:26:50 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 351FQeKd050914; Thu, 1 Jun 2023 10:26:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685633200; bh=1FxEiq4IJPrUO7dOCsKlrtj2JEqc2+hWqd9SUqfLYNA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xPwv6qCmREJPNvxvJrKxbX9VgYhjAOdYXUKWTZnfz6y8DZwlb7Kejfk3z/p3t8jQT 9E9Vek95mV/BqqVZaxtOc3UdSfNfucwClSQNqT/RavyBk7u4ZBYzcXG4YGzCBuzTe1 gf7yRzk51sUPMO/TjMbZajYqO2HVCSlWoaEB9os0= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 351FQeHj086518 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 Jun 2023 10:26:40 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 10:26:39 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 10:26:39 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 351FQd4q017628; Thu, 1 Jun 2023 10:26:39 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring CC: , , , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , Udit Kumar Subject: [PATCH 02/12] arm64: dts: ti: k3-j721e-som-p0/common-proc-board: Fixup reference to phandles array Date: Thu, 1 Jun 2023 10:26:26 -0500 Message-ID: <20230601152636.858553-3-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230601152636.858553-1-nm@ti.com> References: <20230601152636.858553-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 4 ++-- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 18 +++++++++--------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 23f242ab6aa3..25111c86511f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -25,7 +25,7 @@ gpio_keys: gpio-keys { compatible = "gpio-keys"; autorepeat; pinctrl-names = "default"; - pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; + pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>; sw10: switch-10 { label = "GPIO Key USER1"; @@ -701,7 +701,7 @@ exp5: gpio@20 { &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 51a57d34ebea..a0be8d2edac6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -271,55 +271,55 @@ mbox_c71_0: mbox-c71-0 { }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; };