From patchwork Fri Jun 2 09:02:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 688888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F10C0C7EE24 for ; Fri, 2 Jun 2023 09:05:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233705AbjFBJFD (ORCPT ); Fri, 2 Jun 2023 05:05:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234887AbjFBJEO (ORCPT ); Fri, 2 Jun 2023 05:04:14 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58B0210D3; Fri, 2 Jun 2023 02:03:52 -0700 (PDT) X-UUID: 627c4b5c012411eeb20a276fd37b9834-20230602 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=DCFWUdjviYmmYlgFSnIU9vsT+vPlbuNQol0JggDKPBM=; b=lw+FNxwTOMotQdSr4V1hXqd3Dqep/NAgLF7TUjpQEZyfalYSnb/1XSGa8Fzo79xuXHse9DatzhFWovpVzrM0lLfBqonT0E3Ig4Ik5Q+iCeGnFxwBGV2tnQJRlRnVx+MWJ/1Tf7IQ9YfqDndGoW5tOyiGN/GbE2uu2Cbx0Q/ymZk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.25, REQID:87e092fa-e6b3-49e4-a637-ba4bc1fc6ac2, IP:0, U RL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:75 X-CID-INFO: VERSION:1.1.25, REQID:87e092fa-e6b3-49e4-a637-ba4bc1fc6ac2, IP:0, URL :0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:75 X-CID-META: VersionHash:d5b0ae3, CLOUDID:17c65f3d-7aa7-41f3-a6bd-0433bee822f3, B ulkID:2306021703480TSGZL2J,BulkQuantity:0,Recheck:0,SF:48|38|29|28|17|19,T C:nil,Content:1,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 627c4b5c012411eeb20a276fd37b9834-20230602 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1077349802; Fri, 02 Jun 2023 17:03:47 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 2 Jun 2023 17:03:46 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 2 Jun 2023 17:03:45 +0800 From: Yong Wu To: Joerg Roedel , Will Deacon , Rob Herring , Matthias Brugger CC: Robin Murphy , Krzysztof Kozlowski , Yong Wu , AngeloGioacchino Del Regno , , , , , , , , , Subject: [PATCH v12 6/7] iommu/mediatek: mt8188: Add iova_region_larb_msk Date: Fri, 2 Jun 2023 17:02:26 +0800 Message-ID: <20230602090227.7264-7-yong.wu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230602090227.7264-1-yong.wu@mediatek.com> References: <20230602090227.7264-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add iova_region_larb_msk for mt8188. We separate the 16GB iova regions by each device's larbid/portid. Refer to include/dt-bindings/memory/mediatek,mt8188-memory-port.h As commented in the code, larb19(21) means it's larb19 while its SW index is 21. Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5c66af0c45a8..b17d3e7288a7 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -1606,6 +1606,20 @@ static const struct mtk_iommu_plat_data mt8188_data_infra = { .iova_region_nr = ARRAY_SIZE(single_domain), }; +static const u32 mt8188_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { + [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */ + [1] = {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, ~0, ~0, ~0}, /* Region1: larb19(21)/21(22)/23 */ + [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */ + ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, + ~0, ~0, ~0, ~0, ~0, 0, 0, 0, + 0, ~0}, + [3] = {0}, + [4] = {[24] = BIT(0) | BIT(1)}, /* Only larb27(24) port0/1 */ + [5] = {[24] = BIT(2) | BIT(3)}, /* Only larb27(24) port2/3 */ +}; + static const struct mtk_iommu_plat_data mt8188_data_vdo = { .m4u_plat = M4U_MT8188, .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | @@ -1617,6 +1631,7 @@ static const struct mtk_iommu_plat_data mt8188_data_vdo = { .banks_enable = {true}, .iova_region = mt8192_multi_dom, .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), + .iova_region_larb_msk = mt8188_larb_region_msk, .larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10, 11 /* 11a */, 25 /* 11c */}, {13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}}, @@ -1633,6 +1648,7 @@ static const struct mtk_iommu_plat_data mt8188_data_vpp = { .banks_enable = {true}, .iova_region = mt8192_multi_dom, .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), + .iova_region_larb_msk = mt8188_larb_region_msk, .larbid_remap = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID}, {12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID, 16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID,