From patchwork Sat Jun 3 20:02:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 688828 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59231C77B7A for ; Sat, 3 Jun 2023 20:07:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230385AbjFCUHy (ORCPT ); Sat, 3 Jun 2023 16:07:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230345AbjFCUHx (ORCPT ); Sat, 3 Jun 2023 16:07:53 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9253E7A; Sat, 3 Jun 2023 13:07:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685822846; x=1717358846; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kR+GAFxGqayegRnGgFCafROzzdAvlW1/3P/cmAH1gx4=; b=z5dHuobx+LF8bCDK/MmJYQ4T3Bv8jl/fz/2FWfLYw6mr74fC9vRcN2Hy gj93XlBFZr6dYUxyGGq2m6zSi4vNMRFmYqDQ0DERjFOuulYEUczQiTxMW 3Rshp+05gklZU4bDI6sahydpCYLodcHA4h9k5lcHcTW8OobYTNQ8LrZ1f a+enyFoVe16881zPCMwWPptx/N/6MBOjm+J3yusG/KZrNh/XXAzbiKbk3 1BU4bQqlYaIBVW7ZRo53QhhuLwTDnJXCycoysF1klwZvcVcV54V+GAimr qKJiFp0Kmxxc/1rmJCC/JxxL39GS6IiOg5oNm2PmnDgt/m+kdkyvMU37C A==; X-IronPort-AV: E=Sophos;i="6.00,216,1681196400"; d="scan'208";a="214485477" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:06:23 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:06:22 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:06:10 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic Date: Sun, 4 Jun 2023 01:32:37 +0530 Message-ID: <20230603200243.243878-16-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the support added for the Advanced interrupt controller(AIC) chip in the sam9x7 soc family Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt index 7079d44bf3ba..2c267a66a3ea 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt @@ -4,7 +4,7 @@ Required properties: - compatible: Should be: - "atmel,-aic" where can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" - - "microchip,-aic" where can be "sam9x60" + - "microchip,-aic" where can be "sam9x60", "sam9x7" - interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. It should be 3.