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Sun, 25 Jun 2023 12:37:56 +0000 From: "Peng Fan (OSS)" To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan , Haibo Chen , Ye Li Subject: [PATCH 02/10] arm64: dts: imx8ulp: set default clock for SDHC Date: Sun, 25 Jun 2023 20:42:30 +0800 Message-Id: <20230625124238.4071717-3-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230625124238.4071717-1-peng.fan@oss.nxp.com> References: <20230625124238.4071717-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0111.apcprd01.prod.exchangelabs.com (2603:1096:4:40::15) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|AS4PR04MB9314:EE_ X-MS-Office365-Filtering-Correlation-Id: 439656e8-fe65-4b52-a672-08db7579003a X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The PLL3 PFD2 maximum frequency is 332Mhz, we can't set it to 389Mhz as USDHC clock parent. Because PLL3 PFD0 is used for NIC, PFD1 is used for audio, the only choice is PFD3 which can reach to 400Mhz. USDHC1 and USDHC2 maximum PCC clock rate is 200Mhz in Over Drive mode, and 100Mhz in Nominal/Low Drive mode, when PTE or PTF is used. The patch adjusts clock parent to PLL3 PFD3 DIV1 for USDHC0, PLL3 PFD3 DIV2 for USDHC1 and USDHC2. And set the max rate to meet restrictions. Signed-off-by: Haibo Chen Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 8116d6eeb738..ba0edb9a009b 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -370,6 +370,10 @@ usdhc0: mmc@298d0000 { <&pcc4 IMX8ULP_CLK_USDHC0>; clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>, + <&pcc4 IMX8ULP_CLK_USDHC0>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>; + assigned-clock-rates = <389283840>, <389283840>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>; @@ -385,6 +389,10 @@ usdhc1: mmc@298e0000 { <&pcc4 IMX8ULP_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, + <&pcc4 IMX8ULP_CLK_USDHC1>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; + assigned-clock-rates = <194641920>, <194641920>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>; @@ -400,6 +408,10 @@ usdhc2: mmc@298f0000 { <&pcc4 IMX8ULP_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, + <&pcc4 IMX8ULP_CLK_USDHC2>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; + assigned-clock-rates = <194641920>, <194641920>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>;