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[82.31.201.19]) by smtp.gmail.com with ESMTPSA id c15-20020adffb4f000000b00313e4d02be8sm15745722wrs.55.2023.06.29.14.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 14:01:02 -0700 (PDT) From: Caleb Connolly Date: Thu, 29 Jun 2023 22:00:53 +0100 Subject: [PATCH v2 1/3] arm64: dts: qcom: c630: add panel bridge 1p2 regulator MIME-Version: 1.0 Message-Id: <20230627-c630-uart-and-1p2-reg-v2-1-496b581935c1@linaro.org> References: <20230627-c630-uart-and-1p2-reg-v2-0-496b581935c1@linaro.org> In-Reply-To: <20230627-c630-uart-and-1p2-reg-v2-0-496b581935c1@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Caleb Connolly X-Mailer: b4 0.13-dev-46309 X-Developer-Signature: v=1; a=openpgp-sha256; l=1858; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=L2itCOUfvSzeXSASQubMcjpUvnUlL8UMtdvpzAwhCKM=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBknfEMJxqxd24gGIVNHXSSY3H2LmK0s0cNftoX1 L/C5SKUyAiJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZJ3xDAAKCRAFgzErGV9k tu64D/0XmgmNjI40YvCMuw+w5Cc+zpXx1VymQQXb/vjlmJQXzKNWlzjh8MII3e3BShGXQdf0KCw 71BuCQiecPNudev6Hru2zh+2Ov5edxd5X6q8VB2p5rF3uFQ54W9ltW/e4Wc68JAH6IfVTISo+mo 1hKgKPe+bvUymey19Py/pGP9d58Vsqo/lC7Ae6PXzxSWRQt9dI1NUTjPjYybsqJrl39m3ep+4r5 9ViBNMecK3G0U0TzU4bY2japo2+gbMt4zOj293sJlrCwhXp1gn2QDLTE5ozFrBPW5igsjDJ+7Wv Ic5hhIoLjFM5AOMK05cfsU9A+KH2aGpZ7NGyNT8yPGL2sFa2fMxoLHUT1P5d9eIDxg9cL+7aW16 3FG3zrfy7UqEqFCXQb3ZE+kMurFysmn0ugrBVQfbFJQgjgQtvilyUQ9gkqmIQxVlTesF+HfNT1K EB3DGnFXf9WKpH8t+KYPM9gs7XsEsubbVPJKQ1NwNLuW85pkE8V1H94LCNNYIl6P8IG8qDmemkd 2VwhL8mdRlU/iKY43bymD6X0qy7Y+IRsQSnNaPlCuE2ugrXm61w00asX1T1RtaQvF9HNo2/42Hj JRF86v6I5W3xkB5QO1nkMRxD9YTRnGcUkyfqupWR5TDPDdSQdNfgh5zTyjDwp3isLOXfx+dAVfb G7/aoqfeidt1y5Q== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The VCC and VCCA supplies of the DSI<->eDP bridge are derived from vreg_l2a_1p2 and controlled by a GPIO on the PMIC. Add the regulator here so Linux can control it. Signed-off-by: Caleb Connolly --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 22a7d997cdb0..86030771d685 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -80,6 +80,22 @@ adsp_mem: memory@8c600000 { }; }; + sw_edp_1p2: edp-1p2-regulator { + compatible = "regulator-fixed"; + regulator-name = "sw_edp_1p2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + pinctrl-0 = <&sw_edp_1p2_en>; + pinctrl-names = "default"; + + gpio = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_l2a_1p2>; + }; + sn65dsi86_refclk: sn65dsi86-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -425,6 +441,8 @@ sn65dsi86: bridge@2c { enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + vcca-supply = <&sw_edp_1p2>; + vcc-supply = <&sw_edp_1p2>; vpll-supply = <&vreg_l14a_1p88>; vccio-supply = <&vreg_l14a_1p88>; @@ -500,6 +518,16 @@ &mss_pil { firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn"; }; +&pm8998_gpios { + /* This pin is pulled down by a fixed resistor */ + sw_edp_1p2_en: pm8998-gpio9-state { + pins = "gpio9"; + function = "normal"; + bias-disable; + qcom,drive-strength = <0>; + }; +}; + &qup_i2c10_default { drive-strength = <2>; bias-disable;