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Fri, 30 Jun 2023 00:38:50 -0500 From: Sarath Babu Naidu Gaddam To: , , , , , CC: , , , , , , , , , , , Subject: [PATCH net-next V4 1/3] dt-bindings: net: xlnx,axi-ethernet: Introduce DMA support Date: Fri, 30 Jun 2023 11:08:42 +0530 Message-ID: <20230630053844.1366171-2-sarath.babu.naidu.gaddam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com> References: <20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT025:EE_|BN9PR12MB5227:EE_ X-MS-Office365-Filtering-Correlation-Id: 67bed9fa-1f78-44fa-f8f6-08db792c55ff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hA3WI+vHy7sKsMz8kt/fCmw4Yysll1iJaKwMWxaQIclboqYrir3ZSktNp40qZmXlW0r43DxwNzdE5Lg3A6AaY/iclJRivkIxFnzC/H4du7uz0KK1Dy2Ntkx89rEHUxKLnYQVgadWgaASCtweilHyb1ZRK3nWfEF9l0okFw6J9jyi92knO61eZHW95fKt7dogz43UsQYyom23zXmYVnqmNVSm70zcAXf4JLgBfwPpQVl0xE78U8Kr8BvQlQ/wWpRn38+H2+eTlC+0d48hQt3Z7pbq1SfYYFTHN9m+f5/tj9ZmbQVTevqHe6aSOJDA1VawYuxaLgPf7WZmmiqAQDXTtwO3PxiHuZTGtNH0NCpQ7gPOpmKjshNaU2D2Rd2O14e+3J4qzdGwpCQurnp1koc2eURMQhdPsmPMMW6OLL9sn5S8HRU7lmXo0fxvHzsP3gvqiHqrb9ePaM1mgbvJX62qHgv1ep65nRzSyMP5GRqFBMgH5sebm+VPgTyOi6oPvwXKw8hjQ9FUqhbDDTCqKbIdmoaq14GYkDgCvFXX/cArRGQNLnCh6MhFy0WrEblrgwv7Kn1IOJzz73wyuJVoZRvWe4sBtYJroupBFEzdJddAsXiKz8BJ5CIrjUp7eKXeuw5YbaUeT0cBTkAoz2nqBqEpdEISvj/lJsfQ8K4z5Mdh+NGi8qL/ad5QlNkWYnXhEBfXuIigqBBk9CI5iJNjJmLoCXoJWSvLipw881G07VPRF/dYq7fNnuStAXlnqGT84zzvx+rvznDmLK6Rd5Khj2Czow== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(396003)(376002)(346002)(136003)(39860400002)(451199021)(36840700001)(46966006)(40470700004)(8676002)(316002)(70206006)(186003)(4326008)(26005)(1076003)(336012)(8936002)(110136005)(54906003)(40460700003)(6666004)(41300700001)(70586007)(82310400005)(5660300002)(7416002)(2906002)(40480700001)(478600001)(2616005)(81166007)(356005)(82740400003)(103116003)(86362001)(83380400001)(36860700001)(36756003)(47076005)(426003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2023 05:39:13.0636 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67bed9fa-1f78-44fa-f8f6-08db792c55ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5227 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Radhey Shyam Pandey The axiethernet will use dmaengine framework to communicate with dma controller IP instead of built-in dma programming sequence. To request dma transmit and receive channels the axiethernet uses generic dmas, dma-names properties. Axiethernet may use AXI DMA or MCDMA. DMA has only two channels where as MCDMA has 16 Tx, 16 Rx channels. To uniquely identify each channel, we are using 'chan' suffix. Depending on the usecase AXI ethernet driver can request any combination of multichannel DMA channels. Example: dma-names = tx_chan0, rx_chan0, tx_chan1, rx_chan1; Also to support the backward compatibility, use "dmas" property to identify as it should use dmaengine framework or legacy driver(built-in dma programming). At this point it is recommended to use dmaengine framework but it's optional. Once the solution is stable will make dmas as required properties. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Sarath Babu Naidu Gaddam --- Changes in V4: 1) Updated commit description about tx/rx channels name. 2) Removed "dt-bindings" and "dmaengine" strings in subject. 3) Extended dmas and dma-names to support MCDMA channel names. 1) Remove "driver" from commit message. 2) Use pattern/regex for dma-names property. Changes in V3: 1) Reverted reg and interrupts property to support backward compatibility. 2) Moved dmas and dma-names properties from Required properties. Changes in V2: - None. --- .../bindings/net/xlnx,axi-ethernet.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml index 1d33d80af11c..ea203504b8d4 100644 --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml @@ -122,6 +122,20 @@ properties: and "phy-handle" should point to an external PHY if exists. maxItems: 1 + dmas: + minItems: 2 + maxItems: 32 + description: DMA Channel phandle and DMA request line number + + dma-names: + items: + pattern: "^[tr]x_chan[0-9]|1[0-5]$" + description: + Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel + Should be "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel + minItems: 2 + maxItems: 32 + required: - compatible - interrupts @@ -143,6 +157,8 @@ examples: clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>; phy-mode = "mii"; reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>; + dmas = <&xilinx_dma 0>, <&xilinx_dma 1>; + dma-names = "tx_chan0", "rx_chan0"; xlnx,rxcsum = <0x2>; xlnx,rxmem = <0x800>; xlnx,txcsum = <0x2>;