Message ID | 20230703-topic-8250_qup_icc-v1-1-fea39aa07525@linaro.org |
---|---|
State | New |
Headers | show |
Series | Add interconnects to QUPs on SM8250 | expand |
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml index 2e20ca313ec1..2890c4968c2a 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -49,11 +49,16 @@ properties: maxItems: 3 interconnect-names: - minItems: 2 - items: - - const: qup-core - - const: qup-config - - const: qup-memory + oneOf: + - items: + - const: qup-config + - const: qup-memory + + - minItems: 2 + items: + - const: qup-core + - const: qup-config + - const: qup-memory interrupts: maxItems: 1
Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path. Allow such case. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- .../devicetree/bindings/spi/qcom,spi-geni-qcom.yaml | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)