Message ID | 20230703-topic-8250_qup_icc-v1-3-fea39aa07525@linaro.org |
---|---|
State | New |
Headers | show |
Series | Add interconnects to QUPs on SM8250 | expand |
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index 9f66a3bb1f80..f92b6d7fc7c5 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -108,14 +108,25 @@ allOf: clock-names: const: se - interconnects: - minItems: 3 - - interconnect-names: - items: - - const: qup-core - - const: qup-config - - const: qup-memory + oneOf: + - properties: + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: qup-config + - const: qup-memory + + - properties: + interconnects: + minItems: 3 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + - const: qup-memory unevaluatedProperties: false
Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path. Allow such case. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 27 +++++++++++++++------- 1 file changed, 19 insertions(+), 8 deletions(-)