From patchwork Fri Jul 21 20:37:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87?= X-Patchwork-Id: 705063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16994C00528 for ; Fri, 21 Jul 2023 21:12:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230118AbjGUVMD (ORCPT ); Fri, 21 Jul 2023 17:12:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229451AbjGUVMD (ORCPT ); Fri, 21 Jul 2023 17:12:03 -0400 X-Greylist: delayed 343 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 21 Jul 2023 14:11:57 PDT Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D08330E2; Fri, 21 Jul 2023 14:11:57 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id C2ED386D1E; Fri, 21 Jul 2023 23:06:13 +0200 (CEST) From: =?utf-8?q?Duje_Mihanovi=C4=87?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_=87__=3Cduje=2Emihanovic=40sko?= =?unknown-8bit?q?le=2Ehr=3E=2C_linux-clk=40vger=2Ekernel=2Eorg=2C_devicetre?= =?unknown-8bit?q?e=40vger=2Ekernel=2Eorg=2C_linux-kernel=40vger=2Ekernel=2E?= =?unknown-8bit?q?org?= Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com Subject: [PATCH 06/10] dt-bindings: clock: Add documentation for Marvell PXA1908 Date: Fri, 21 Jul 2023 22:37:48 +0200 Message-ID: <20230721210042.21535-7-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dt bindings and documentation for Marvell PXA1908's clock controller blocks. Signed-off-by: Duje Mihanović --- .../bindings/clock/marvell,pxa1908.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 000000000000..3fa6f00a26f7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanović + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, MPMU + and APMU roughly corresponding to internal buses. + + Each clock is assigned an identifier and client nodes use this identifier to + specify the clock which they consume. + + All these identifiers could be found in . + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + reg: + maxItems: 1 + description: | + Physical address of the clock controller and length of the memory mapped + region. + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible = "marvell,pxa1908-apmu"; + reg = <0xd4282800 0x400>; + #clock-cells = <1>; + };