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[83.30.147.116]) by smtp.gmail.com with ESMTPSA id o2-20020a05651238a200b004fbcd542888sm1688366lft.60.2023.07.23.07.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Jul 2023 07:07:39 -0700 (PDT) From: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , AngeloGioacchino Del Regno , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] clk: qcom: hfpll: Add MSM8976 PLL data Date: Sun, 23 Jul 2023 16:06:52 +0200 Message-Id: <20230723140712.9438-6-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230723140712.9438-1-a39.skl@gmail.com> References: <20230723140712.9438-1-a39.skl@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL. Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz. For simplicity only add second range as smaller frequencies can be obtained via apcs divider or safe parent this also saves us a hassle of reconfiguring VCO bit and config_val. A72 and CCI cluster only use single frequency range with their outputs/post_dividers/vco_bits being static. Signed-off-by: Adam Skladowski --- drivers/clk/qcom/hfpll.c | 54 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c index ec18bc8f0089..a9c4c77e0f50 100644 --- a/drivers/clk/qcom/hfpll.c +++ b/drivers/clk/qcom/hfpll.c @@ -32,8 +32,62 @@ static const struct hfpll_data hdata = { .max_rate = 2900000000UL, }; +static const struct hfpll_data msm8976_a53 = { + .mode_reg = 0x00, + .l_reg = 0x04, + .m_reg = 0x08, + .n_reg = 0x0c, + .user_reg = 0x10, + .config_reg = 0x14, + .config_val = 0x341600, + .status_reg = 0x1c, + .lock_bit = 16, + + .l_val = 0x35, + .user_val = 0x109, + .min_rate = 902400000UL, + .max_rate = 1478400000UL, +}; + +static const struct hfpll_data msm8976_a72 = { + .mode_reg = 0x00, + .l_reg = 0x04, + .m_reg = 0x08, + .n_reg = 0x0c, + .user_reg = 0x10, + .config_reg = 0x14, + .config_val = 0x4e0405d, + .status_reg = 0x1c, + .lock_bit = 16, + + .l_val = 0x3e, + .user_val = 0x100109, + .min_rate = 940800000UL, + .max_rate = 1843200000UL, +}; + +static const struct hfpll_data msm8976_cci = { + .mode_reg = 0x00, + .l_reg = 0x04, + .m_reg = 0x08, + .n_reg = 0x0c, + .user_reg = 0x10, + .config_reg = 0x14, + .config_val = 0x141400, + .status_reg = 0x1c, + .lock_bit = 16, + + .l_val = 0x20, + .user_val = 0x100109, + .min_rate = 556800000UL, + .max_rate = 902400000UL, +}; + static const struct of_device_id qcom_hfpll_match_table[] = { { .compatible = "qcom,hfpll", &hdata }, + { .compatible = "qcom,hfpll-msm8976-a53", &msm8976_a53 }, + { .compatible = "qcom,hfpll-msm8976-a72", &msm8976_a72 }, + { .compatible = "qcom,hfpll-msm8976-cci", &msm8976_cci }, { } }; MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);