From patchwork Fri Jul 28 10:28:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 708066 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01EF9C0015E for ; Fri, 28 Jul 2023 10:30:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234608AbjG1KaF (ORCPT ); Fri, 28 Jul 2023 06:30:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234663AbjG1K3h (ORCPT ); Fri, 28 Jul 2023 06:29:37 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE0FF4681; Fri, 28 Jul 2023 03:28:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1690540109; x=1722076109; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=l613YqgfVuGo3pS10BGjJIxh4OsrJCawGN17F2E8C7Q=; b=VW/rWcyFKb0mis+rGt9uVD+6HBwq8bb23ynbJF9Uqmd30nEaaPoRjHMW Ji2VFEt0zlf06AYTjMQ5l1L8ltIsGPMRP3Rpxi7Wif12xIW1SfF5zE5eV Y8eWHBKePmX17sAS7KMVosYDhd6itoRIv6trijm88Q6ZtxKPXS76eafFm uVQr1SJGG8P3NViDaRHlygFH0PIQnPx+Ht0FjPX/2Ryg4yV++Gzqc9Qk5 IApvTWmd0br8EErZ9f5aoQ+8sLBgdmbbcqIE0/MtfiqnifHyBslFmAvB/ bSSGmL8VSUXH8AQTKZL+qvwYY5iD4+QcX3bfnjZvc2/1FOZA6KADpdwXL Q==; X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="226623323" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jul 2023 03:28:27 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 28 Jul 2023 03:28:18 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 28 Jul 2023 03:28:14 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: Subject: [PATCH v3 29/50] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic Date: Fri, 28 Jul 2023 15:58:11 +0530 Message-ID: <20230728102811.266759-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the support added for the Advanced interrupt controller(AIC) chip in the sam9x7 SoC family. Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt index 7079d44bf3ba..5fb9366c94a1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt @@ -4,7 +4,7 @@ Required properties: - compatible: Should be: - "atmel,-aic" where can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" - - "microchip,-aic" where can be "sam9x60" + - "microchip,-aic" where can be "sam9x60" or "sam9x7" - interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. It should be 3.