From patchwork Mon Sep 18 19:21:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 724231 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39D0321101 for ; Mon, 18 Sep 2023 19:22:18 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E191126; Mon, 18 Sep 2023 12:22:12 -0700 (PDT) X-UUID: a8ad3d0a565811eea33bb35ae8d461a2-20230919 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=bUYBgtftoQP8FosQUXrBMLkP++zothKvc1aH24DtKBA=; b=qri/ha5HR9qIAu1NVDSBkBUaacqWgYIj1yJ1PpYH4d3rWeFK9QuSRCzKpwsaDMDwmPDgb7NpxW4pvvINKX4/cfDxJbm9/Jyt3qKZ+zvH3lq8rq6aDuj0foq2awZ9Zni7DR1uMc6qK1Blc+/MOwc7F3tk5gnKIaUAk65KQI0dQ84=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31, REQID:376a802c-c561-490c-86e4-c451a0fad702, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4, CLOUDID:ec9a2bc3-1e57-4345-9d31-31ad9818b39f, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: a8ad3d0a565811eea33bb35ae8d461a2-20230919 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 212089839; Tue, 19 Sep 2023 03:22:08 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 19 Sep 2023 03:22:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 19 Sep 2023 03:22:06 +0800 From: Jason-JH.Lin To: Jassi Brar , Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Conor Dooley , Jason-ch Chen , Johnson Wang , Elvis Wang , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , , , , , , Subject: [PATCH 03/15] soc: mailbox: Add SPR definition for GCE Date: Tue, 19 Sep 2023 03:21:52 +0800 Message-ID: <20230918192204.32263-4-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230918192204.32263-1-jason-jh.lin@mediatek.com> References: <20230918192204.32263-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS,T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net GCE has specific purpose registers, abbreviated as SPR. Client can us SPR to store data or programs. In CMDQ driver, it allows client to STORE or LOAD data into SPR. The value stored in SPR will be cleared after reset GCE HW thread. There are 4 SPR (register index 0 - 3) in every GCE HW thread. SPR is thread-independent and HW secure protected. Signed-off-by: Jason-JH.Lin --- include/linux/soc/mediatek/mtk-cmdq.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 649955d2cf5c..f49ca8bd58e8 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -11,6 +11,11 @@ #include #include +#define CMDQ_THR_SPR_IDX0 0 +#define CMDQ_THR_SPR_IDX1 1 +#define CMDQ_THR_SPR_IDX2 2 +#define CMDQ_THR_SPR_IDX3 3 + #define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0))) #define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1))