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Tue, 3 Oct 2023 12:36:23 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , , , , , Krzysztof Kozlowski Subject: [PATCH v7 RESEND 2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Date: Tue, 3 Oct 2023 23:04:52 +0530 Message-ID: <20231003173453.938190-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231003173453.938190-1-thippeswamy.havalige@amd.com> References: <20231003173453.938190-1-thippeswamy.havalige@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|CH3PR12MB8211:EE_ X-MS-Office365-Filtering-Correlation-Id: 95ea5ea8-0817-4079-2979-08dbc4374683 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: KsbYsN5AsnjnK5bzHUezgNnUO6tqzTiaaqydrt826jHFAPpkj3j1RWNF18hObzsx+P3kv32WBdHJhCxClPLZ2sAinOVAWLAiFf0r6MoGePpTHhVYJrCf/LFasOZazH2PRudlQmHxykHIaJRLMe81e4rstTQbTidtIDvTAG47j4oifP3TlWpAMdUL6xIZxjNiT65LoHWmiYlYCA5NJnUstMyXQWtG25/jkLyVEhLHnNbiTcUGuVZ/5IXPx3RMcmI1ANt3YpJrbOfJZYPPwIyVoClGbYA9Xss9HeTbSFFuI7HBgydazRUrWMHgxIvBNdhMuukcHrttyckP9PJ8kgvz8EEPf6mmXJHIuxuqbcBxr+VE9W2QxQD0xnZHxMSr0z9h0TN7NzRafMSh/C8AZFz8WFgIAFOzzjGEXaZplhjkBGLrgJ8uc8j8NvM63P0SDqeo5MyqbxsVLcLUt1xgdjOKGeBayLF59k8KinoDcRIVeMU5IpJbPTJO3fpZrmw5aYOVvmpBWzvi/gcXZpswICeN8cNWjbuawS2xKMdoKOEgo3/+EzlbD4wSJVSlDKqB9VVBxpFMltiE3VCyYfr9DebnFF2SShCMIBcvhj4NBkE88JXItMvtP61cwBmYzbIxgVVzeknsoTQa4j97Zkj3cM23WjVJIt41RxrOqh5GLFHyiLhCiL+IZrL+7mtQdxSDQ1hu8/FeE8g1t8q5ulr203CAcp3om85pvUBRH2jE0T5iwbFw/kl2yB7kfnqvFKlF3oWtFHU0BqIlNKk6O8EvQtHdxYaXR3mi2t++yaGzxW/UnEnm/nMG03CjTCwYz/B8sZiM X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8211 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add YAML dtschemas of Xilinx XDMA Soft IP PCIe Root Port Bridge dt binding. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- changes in v7: - None changes in v6: - None change in v5: - Modified uppercase case hex value to lower case. change in v4: - Removed unnecessary space. changes in v3: - Fixed compatible string issue. - Modified ranges property description to maxItems. - Modified address-cell property of interrupt-controller child node. changes in v2: - None --- .../bindings/pci/xlnx,xdma-host.yaml | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml new file mode 100644 index 000000000000..0aa00b8e49b3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx XDMA PL PCIe Root Port Bridge + +maintainers: + - Thippeswamy Havalige + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: xlnx,xdma-host-3.00 + + reg: + maxItems: 1 + + ranges: + maxItems: 2 + + interrupts: + items: + - description: interrupt asserted when miscellaneous interrupt is received. + - description: msi0 interrupt asserted when an MSI is received. + - description: msi1 interrupt asserted when an MSI is received. + + interrupt-names: + items: + - const: misc + - const: msi0 + - const: msi1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + properties: + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + required: + - interrupt-controller + - "#address-cells" + - "#interrupt-cells" + + additionalProperties: false + +required: + - compatible + - reg + - ranges + - interrupts + - interrupt-map + - interrupt-map-mask + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@a0000000 { + compatible = "xlnx,xdma-host-3.00"; + reg = <0x0 0xa0000000 0x0 0x10000000>; + ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>, + <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = , , + ; + interrupt-names = "misc", "msi0", "msi1"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + };