[04/12] clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable

Message ID	20231218-topic-8550_fixes-v1-4-ce1272d77540@linaro.org
State	Accepted
Commit	e7fe73fc6b68ee97b1e8f124a66a5ee50d8d5e5b
Headers	show Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAFD05A85F for <devicetree@vger.kernel.org>; Mon, 18 Dec 2023 16:02:25 +0000 (UTC) From: Konrad Dybcio <konrad.dybcio@linaro.org> Date: Mon, 18 Dec 2023 17:02:05 +0100 Subject: [PATCH 04/12] clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20231218-topic-8550_fixes-v1-4-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson <andersson@kernel.org>, Georgi Djakov <djakov@kernel.org>, Abel Vesa <abel.vesa@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Taniya Das <quic_tdas@quicinc.com>, Jagadeesh Kona <quic_jkona@quicinc.com>, Neil Armstrong <neil.armstrong@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Sai Prakash Ranjan <quic_saipraka@quicinc.com> Cc: Marijn Suijten <marijn.suijten@somainline.org>, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio <konrad.dybcio@linaro.org>
Series	8550 fixups \| expand [00/12] 8550 fixups [01/12] interconnect: qcom: sm8550: Remove bogus per-RSC BCMs and nodes [02/12] interconnect: qcom: sm8550: Enable sync_state [03/12] clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag [04/12] clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable [05/12] clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs [06/12] clk: qcom: gcc-sm8550: Mark RCGs shared where applicable [07/12] clk: qcom: gpucc-sm8550: Update GPU PLL settings [08/12] clk: qcom: dispcc-sm8550: Update disp PLL settings [09/12] clk: qcom: dispcc-sm8550: Use the correct PLL configuration function [10/12] arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2 [11/12] arm64: dts: qcom: sm8550: Separate out X3 idle state [12/12] arm64: dts: qcom: sm8550: Update idle state time requirements

Message ID

20231218-topic-8550_fixes-v1-4-ce1272d77540@linaro.org

State

Accepted

Commit

e7fe73fc6b68ee97b1e8f124a66a5ee50d8d5e5b

Headers

From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 18 Dec 2023 17:02:05 +0100
Subject: [PATCH 04/12] clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable
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Message-Id: <20231218-topic-8550_fixes-v1-4-ce1272d77540@linaro.org>
References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org>
In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org>
To: Bjorn Andersson <andersson@kernel.org>,
 Georgi Djakov <djakov@kernel.org>, Abel Vesa <abel.vesa@linaro.org>,
 Michael Turquette <mturquette@baylibre.com>,
 Stephen Boyd <sboyd@kernel.org>, Taniya Das <quic_tdas@quicinc.com>,
 Jagadeesh Kona <quic_jkona@quicinc.com>,
 Neil Armstrong <neil.armstrong@linaro.org>,
 Rob Herring <robh+dt@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Conor Dooley <conor+dt@kernel.org>,
 Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
 linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
 devicetree@vger.kernel.org, Konrad Dybcio <konrad.dybcio@linaro.org>

Series

8550 fixups | expand

Commit Message

Konrad Dybcio Dec. 18, 2023, 4:02 p.m. UTC

The PCIe GDSCs on most Qualcomm platforms expect the OS to always
consider collapse requests as successful. This also concerns SM8550.

Add the VOTABLE flag to the GDSCs in question to comply with these
expectations.

Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/clk/qcom/gcc-sm8550.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index 1c3d78500392..a16d07426b71 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -3002,7 +3002,7 @@  static struct gdsc pcie_0_gdsc = {
 		.name = "pcie_0_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
-	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
 static struct gdsc pcie_0_phy_gdsc = {
@@ -3011,7 +3011,7 @@  static struct gdsc pcie_0_phy_gdsc = {
 		.name = "pcie_0_phy_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
-	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
 static struct gdsc pcie_1_gdsc = {
@@ -3020,7 +3020,7 @@  static struct gdsc pcie_1_gdsc = {
 		.name = "pcie_1_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
-	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
 static struct gdsc pcie_1_phy_gdsc = {
@@ -3029,7 +3029,7 @@  static struct gdsc pcie_1_phy_gdsc = {
 		.name = "pcie_1_phy_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
-	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
 static struct gdsc ufs_phy_gdsc = {

[04/12] clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable

Commit Message

Patch