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[178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:33 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:09 +0100 Subject: [PATCH 08/12] clk: qcom: dispcc-sm8550: Update disp PLL settings Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-8-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=1329; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=5tbiuHAzVzq42DxvRzRnmc/Zm2HLv3YyRRdXfzE5DAk=; b=Ml2SoneCW7eoztQueMMtroWW6FEuyqSxKRQRSzXBES8NAlXPnbPsg4hQNwTHWSOgfF5q8Cj0e USMLm3l023jAJ13fBcautlg7huj/piY49NzF84kNnnyz5Mt5qBm41hx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sm8550.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index aefa19f3c2c5..0b8f0904b339 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -81,6 +81,10 @@ static const struct alpha_pll_config disp_cc_pll0_config = { .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000005, }; @@ -108,6 +112,10 @@ static const struct alpha_pll_config disp_cc_pll1_config = { .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000005, };