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[178.235.179.28]) by smtp.gmail.com with ESMTPSA id fb20-20020a1709073a1400b00a26a061ae1esm6854252ejc.97.2023.12.27.14.28.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 14:28:33 -0800 (PST) From: Konrad Dybcio Date: Wed, 27 Dec 2023 23:28:27 +0100 Subject: [PATCH 2/3] arm64: dts: qcom: sc8280xp: Correct USB PHY power domains Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231227-topic-8280_pcie_dts-v1-2-13d12b1698ff@linaro.org> References: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> In-Reply-To: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Johan Hovold Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703716109; l=1965; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=VmfNU1/o30xTIL8Pi0ZpiDYz44NQF133gdGRmB0j+A0=; b=hkt2IT7RGZcKOjV7EFH8npQu9Q5Lojs0lNc697VJjqDjCIZ3m9BCDB/PTok2jUH2kpcYbGaLK HDW9gz58IuoBeaUtaWlu6ytDk67tB1yKYyVUV8yfVqnYEpj03699D7n X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The USB GDSCs are only related to the controllers. The PHYs on the other hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators. Fix the power-domains assignment to stop potentially toggling the GDSC unnecessarily. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 72c5818b67f2..4b18a0762ca7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2597,7 +2597,7 @@ usb_2_qmpphy0: phy@88ef000 { <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; reset-names = "phy", "phy_phy"; - power-domains = <&gcc USB30_MP_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; #clock-cells = <0>; clock-output-names = "usb2_phy0_pipe_clk"; @@ -2621,7 +2621,7 @@ usb_2_qmpphy1: phy@88f1000 { <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; reset-names = "phy", "phy_phy"; - power-domains = <&gcc USB30_MP_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; #clock-cells = <0>; clock-output-names = "usb2_phy1_pipe_clk"; @@ -3109,7 +3109,7 @@ usb_0_qmpphy: phy@88eb000 { <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", "usb3_pipe"; - power-domains = <&gcc USB30_PRIM_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; @@ -3162,7 +3162,7 @@ usb_1_qmpphy: phy@8903000 { <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", "usb3_pipe"; - power-domains = <&gcc USB30_SEC_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_USB3_PHY_SEC_BCR>, <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;