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[178.235.179.36]) by smtp.gmail.com with ESMTPSA id wj6-20020a170907050600b00a26a0145c5esm8609623ejb.116.2023.12.29.16.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 16:05:15 -0800 (PST) From: Konrad Dybcio Date: Sat, 30 Dec 2023 01:05:07 +0100 Subject: [PATCH 06/10] arm64: dts: qcom: sc8180x: Don't hold MDP core clock at FMAX Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231230-topic-8180_more_fixes-v1-6-93b5c107ed43@linaro.org> References: <20231230-topic-8180_more_fixes-v1-0-93b5c107ed43@linaro.org> In-Reply-To: <20231230-topic-8180_more_fixes-v1-0-93b5c107ed43@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703894704; l=1000; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=M8bX5G9YVihCaiyP4SOPHUALrA9FvX1X19kxYRjo79o=; b=qBSuZww/cfnY6WCaqXkt8K19wXn5NmgDE9scwK/qdrSuoEjfW6DBKSRPSIMJltFQ9bM9hN80C TfujnXtqcQXCxCmejJU+uXloO0bmM/1c6+xqffF22N8PJr0MZPWsIow X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= There's an OPP table to handle this, drop the permanent vote. Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 8f7f5b74cdb9..3bb9d25b1dec 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2732,10 +2732,8 @@ mdss_mdp: mdp@ae01000 { "rot", "lut"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <460000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC8180X_MMCX>;