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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id f15-20020a17090660cf00b00a26f66ce72fsm7941200ejk.83.2024.01.02.12.59.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 12:59:51 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Daniel Golle , Hsin-Yi Wang , =?utf-8?q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= , jason-ch chen , Macpaul Lin , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH 2/2] arm64: dts: mediatek: Add initial MT7988A and BPI-R4 Date: Tue, 2 Jan 2024 21:59:41 +0100 Message-Id: <20240102205941.29654-2-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240102205941.29654-1-zajec5@gmail.com> References: <20240102205941.29654-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Rafał Miłecki MT7988A (AKA MediaTek Filogic 880) is a quad-core ARM Cortex-A73 platform designed for Wi-Fi 7 devices (there is no wireless on SoC though). The first public MT7988A device is Banana Pi BPI-R4. Many SoC parts remain to be added (they need their own bindings or depend on missing clocks). Those present block however are correct and having base .dtsi will help testing & working on missing stuff. Signed-off-by: Rafał Miłecki --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 11 ++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 149 ++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 1e6f91731e92..0a189d5d8006 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts new file mode 100644 index 000000000000..efc4ad0b08b8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; + +#include "mt7988a.dtsi" + +/ { + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; + model = "Banana Pi BPI-R4"; + chassis-type = "embedded"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi new file mode 100644 index 000000000000..0f2ae9c7aef7 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +#include + +/ { + compatible = "mediatek,mt7986a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a73"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a73"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a73"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a73"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + }; + }; + + oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + + pmu { + compatible = "arm,cortex-a73-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ + secmon@43000000 { + reg = <0 0x43000000 0 0x50000>; + no-map; + }; + + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + watchdog@1001c000 { + compatible = "mediatek,mt7988-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + trips { + crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + active-low { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; +};