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[209.132.180.67]) by mx.google.com with ESMTP id f74si19077230pfh.38.2019.02.28.04.28.01; Thu, 28 Feb 2019 04:28:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zpLpTz9E; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731968AbfB1M2A (ORCPT + 7 others); Thu, 28 Feb 2019 07:28:00 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:45912 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731919AbfB1M17 (ORCPT ); Thu, 28 Feb 2019 07:27:59 -0500 Received: by mail-wr1-f65.google.com with SMTP id w17so21717007wrn.12 for ; Thu, 28 Feb 2019 04:27:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=n8wsQ7ixOIiYIm36smSOqEN/oeuVV2Uzvv7QGvE7MK8=; b=zpLpTz9EuHe3H8J6BSqrYGGXTQ59pWPo9uc0KOL3uym5G7IC5wsSariHgQn36HPBDw irV3C4yxFv0bUCagssXQLQIy0m2YSNPGTKxqKZySv5s3rd7ZdtS4pzgtrHTJ+jxnD4yA w0ahKEvSrkGcZWoX6fHpBT7VWPsPHAk04Flh0/4S3VZ08V7gxqAIwKvgongvnVVqg455 sDkKAmvN8kx1fH0/FdjaGEmzORdawyBNWI8bN3GKozOgEGnVFyclIj82+Dxl8o6heTxG 76fmwzxKpOntZM+ED9U0tznDVrlNkQ9bskfhpWts3HtPkgEX2RlAflM8HcKTGUIGniTP /M/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=n8wsQ7ixOIiYIm36smSOqEN/oeuVV2Uzvv7QGvE7MK8=; b=CayCIPhtZ6T/Fv3MZiIr8bP86fp2OHVd0lS54V+q6qAQ4RQdSsnJppFed2CDciRdkD OWlcdxdBj7dS4NBDoe7qkRzDuI9nDsCabvi0G74urgNkwS0GVfNfKiUb71jjs/jIAjnq +xETfo5CMjZoAfMNuiiZiKiJgf+qX9aFYXawB2AqjnsqFxielFgambflM2vmUnxOgAB7 97a+iEkCcAib6xYcXPnSZL/zAEsMnE4NMfIY1LgtkwpGfovHjsn/R7C/RpsiHh7sEnFH gxO1P+9EchGw8LlbaELEuarh+duV7M+0xgJgX2tTFSVuZxsw/j71++pcokh3gyInnt3F 24lQ== X-Gm-Message-State: APjAAAU2s+l8X40NffS6+oK9I3cbcJby6ffcaJ2txaBuqz9bG5YJsiZF kh/joRfj5qjDKZlWQae7x+0+CA== X-Received: by 2002:a05:6000:1084:: with SMTP id y4mr6228423wrw.14.1551356877669; Thu, 28 Feb 2019 04:27:57 -0800 (PST) Received: from localhost ([49.248.54.130]) by smtp.gmail.com with ESMTPSA id a1sm25201268wrq.96.2019.02.28.04.27.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Feb 2019 04:27:56 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 20/24] dt: thermal: tsens: Add bindings for qcs404 Date: Thu, 28 Feb 2019 17:51:10 +0530 Message-Id: <65d1d506388301b88fdc4380897441d3b1d36f90.1551355503.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org qcs404 uses v1 of the TSENS IP block. Create a fallback DT property "qcom,tsens-v1" to gather common code Signed-off-by: Amit Kucheria Reviewed-by: Rob Herring --- .../devicetree/bindings/thermal/qcom-tsens.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt index 1d9e8cf61018..673cc1831ee9 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt @@ -6,11 +6,14 @@ Required properties: - "qcom,msm8916-tsens" (MSM8916) - "qcom,msm8974-tsens" (MSM8974) - "qcom,msm8996-tsens" (MSM8996) + - "qcom,qcs404-tsens", "qcom,tsens-v1" (QCS404) - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998) - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845) The generic "qcom,tsens-v2" property must be used as a fallback for any SoC with version 2 of the TSENS IP. MSM8996 is the only exception because the generic property did not exist when support was added. + Similarly, the generic "qcom,tsens-v1" property must be used as a fallback for + any SoC with version 1 of the TSENS IP. - reg: Address range of the thermal registers. New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM @@ -39,3 +42,14 @@ tsens0: thermal-sensor@c263000 { #qcom,sensors = <13>; #thermal-sensor-cells = <1>; }; + +Example 3 (for any platform containing v1 of the TSENS IP): +tsens: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + };