From patchwork Tue Dec 1 13:21:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 336203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73C46C83012 for ; Tue, 1 Dec 2020 13:22:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 23CDD2084C for ; Tue, 1 Dec 2020 13:22:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=agner.ch header.i=@agner.ch header.b="E8FWOCDF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730179AbgLANWe (ORCPT ); Tue, 1 Dec 2020 08:22:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729676AbgLANWc (ORCPT ); Tue, 1 Dec 2020 08:22:32 -0500 Received: from mail.kmu-office.ch (mail.kmu-office.ch [IPv6:2a02:418:6a02::a2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD415C0617A7; Tue, 1 Dec 2020 05:21:51 -0800 (PST) Received: from allenwind.lan (unknown [IPv6:2a02:169:3df5::979]) by mail.kmu-office.ch (Postfix) with ESMTPSA id C07EF5C2AB7; Tue, 1 Dec 2020 14:21:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=agner.ch; s=dkim; t=1606828909; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OtFe8i1obXmaq2UarSATtwgKWDwPVnyMFK5sF7gJVHo=; b=E8FWOCDF8u8bEc0WDVHeUhTm80cxqxN6gUgJr0snnbvuwDItpg85MqJNozVieUcYOAlJCe /ywDxatSQpyIpArJ3Oh4VKlfausKGG9g2OpDhGyBKQYaatrO/eYT/oiV8RQfctxhVPmLZT BK7N3I0uKpvp5+O931zenfIGPbiWNwg= From: Stefan Agner To: khilman@baylibre.com Cc: robh+dt@kernel.org, narmstrong@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, christianshewitt@gmail.com, jian.hu@amlogic.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan Agner Subject: [PATCH v2 4/5] arm64: dts: meson: g12a: x96-max: fix PHY deassert timing requirements Date: Tue, 1 Dec 2020 14:21:40 +0100 Message-Id: <83c1a57cb99c04dc31098166f0c26073de5e7709.1606828668.git.stefan@agner.ch> X-Mailer: git-send-email 2.29.2 In-Reply-To: <14754fd95378b78eb9a0a3f8b6bab13f7263c7f1.1606828668.git.stefan@agner.ch> References: <14754fd95378b78eb9a0a3f8b6bab13f7263c7f1.1606828668.git.stefan@agner.ch> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY egisters. On similar boards with the same PHY this fixes an issue where Ethernet link would not come up when using ip link set down/up. Fixes: ed5e8f689154 ("arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line") Signed-off-by: Stefan Agner Reviewed-by: Martin Blumenstingl --- arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 1b07c8c06eac..463a72d6bb7c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -340,7 +340,7 @@ external_phy: ethernet-phy@0 { eee-broken-1000t; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; interrupt-parent = <&gpio_intc>;