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[209.132.180.67]) by mx.google.com with ESMTP id y193-v6si1043163pgd.512.2018.08.28.06.39.08; Tue, 28 Aug 2018 06:39:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SOGRxD30; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727385AbeH1Rat (ORCPT + 6 others); Tue, 28 Aug 2018 13:30:49 -0400 Received: from mail-ed1-f67.google.com ([209.85.208.67]:39082 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727342AbeH1Ras (ORCPT ); Tue, 28 Aug 2018 13:30:48 -0400 Received: by mail-ed1-f67.google.com with SMTP id h4-v6so1404364edi.6 for ; Tue, 28 Aug 2018 06:39:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=68+Vu+lQWHojtoyEFuI2o+33g2Xv3HxIF7ejjTszY6c=; b=SOGRxD30exOWpoDV2OGbRamp96wEPhPVG/dSE0/Rhpw1p3uWDu0VB1TU2fztYQduUa NicRk8TODj2x0Sy0bWFRWZLmUm+0RJLKO/Diavtim7ZEBkbSW+5EJ0f4iPqFOm27YJV5 jORaVpjrGWycYExZu6NIsRBFlLOoKcdSaJk5s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=68+Vu+lQWHojtoyEFuI2o+33g2Xv3HxIF7ejjTszY6c=; b=YqfqU3Qx/7xSq3+aq5MbDoS3m5ltgpxdIrfhhCDZ9Chj2mOaZhzNU15N1PZjVJ56cR Q6Le+r1lojW8iTjWNPYPIenJQK8YJ+mJmbtHVr4mh6oMJKs3448dfeL87Ao8FGijJ5oV BUHLFxjJQydQzQfrZYb8kOzRFy5HsVglYSfX7EcWOz61cOMTwyb0zbaaSCwa6YNu+AKP fmLv7NshqnEQBWP94aqw1BQsLxpvb+6MEQdfcz1NB5djv4cfyXCnZlmST3VAnvaPyXDG zknVyz2twBJdyizdHlsJ/ttwAu3c0f1ngJmtHNe8P4EE6ORu5XIMLly8zEd7/3YLqEjG nhJg== X-Gm-Message-State: APzg51Dug9pamDKwdJPLle5MrZ5YldtaUgeu9fX+Bb3SBvf2jGmLdXzo A9y4ZcFQvW3MI8AqVu86FRMRnw== X-Received: by 2002:a50:8ee4:: with SMTP id x33-v6mr2488157edx.252.1535463545430; Tue, 28 Aug 2018 06:39:05 -0700 (PDT) Received: from localhost ([49.248.200.109]) by smtp.gmail.com with ESMTPSA id c28-v6sm722599edc.52.2018.08.28.06.39.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 28 Aug 2018 06:39:04 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, David Brown , Rob Herring , Mark Rutland , Zhang Rui , Daniel Lezcano , linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 01/11] arm/arm64: dts: msm8974/msm8916: thermal: Split address space into two Date: Tue, 28 Aug 2018 19:08:30 +0530 Message-Id: <882739b10bd0a3b655baef9b7ee1958680aa0b04.1535462942.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for the remaining platforms that have a similar register layout and make corresponding changes to the get_temp_common() function used by these platforms. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke --- arch/arm/boot/dts/qcom-msm8974.dtsi | 5 +++-- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- drivers/thermal/qcom/tsens-common.c | 5 +++-- 3 files changed, 9 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index d9019a49b292..56dbbf788d15 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -427,9 +427,10 @@ }; }; - tsens: thermal-sensor@fc4a8000 { + tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a8000 0x2000>; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; #thermal-sensor-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 7b32b8990d62..6a277fce3333 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -761,9 +761,10 @@ }; }; - tsens: thermal-sensor@4a8000 { + tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens"; - reg = <0x4a8000 0x2000>; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; #thermal-sensor-cells = <1>; diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 6207d8d92351..478739543bbc 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -21,7 +21,7 @@ #include #include "tsens.h" -#define S0_ST_ADDR 0x1030 +#define STATUS_OFFSET 0x30 #define SN_ADDR_OFFSET 0x4 #define SN_ST_TEMP_MASK 0x3ff #define CAL_DEGC_PT1 30 @@ -107,8 +107,9 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp) unsigned int status_reg; int last_temp = 0, ret; - status_reg = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET; + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * SN_ADDR_OFFSET; ret = regmap_read(tmdev->map, status_reg, &code); + if (ret) return ret; last_temp = code & SN_ST_TEMP_MASK;